Abstract: A phase-locked loop circuit with dynamic backup is disclosed. The phase-locked loop circuit with dynamic backup includes a phase comparator, a lowpass filter, a voltage-controlled oscillator, and a detection circuit. The phase comparator compares an input reference signal and a feedback output signal from an output of the phase-locked loop circuit for generating a voltage signal representing the phase difference between the input reference signal and the feedback output signal. After the voltage signal is filtered by the lowpass filter, the filtered voltage signal is sent to the voltage-controlled oscillator for generating the feedback output signal. Coupled to the phase comparator, the detection circuit detects whether or not the phase-locked loop circuit is in lock with the input reference signal.

Abstract: A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width.

Abstract: A system and method for communicating information from a high speed digital device, such as a processor, to a high speed peripheral device over a bus which has a frequency capability materially lower than the clock rates of the respective sending and receiving devices. Multiple successive digital signals are latched, converted to analog format current source signals, transmitted over the bus in analog format, decoded into respective digital format signals at the receiving end of the bus, and sequentially provided to the peripheral device in the original order. Analog to digital and digital to analog conversion accuracy is maintained through the use of a linking current reference which defines at each end of the bus a reference signal suitable for mirrored replication. The current mirrors allow accurate integrated circuit device dimension controlled current generation and corresponding current level decoding.