Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data.

Abstract: A device is provided for use with a signal, wherein the device includes a substrate, a first signal trace and a second signal trace. The first signal trace is disposed within the substrate at a first plane from the top surface by a distance d1. The second signal trace is disposed within the substrate at a second plane from the top surface by a distance d2, wherein d2<d1<t. The first signal trace includes a first portion, whereas the second signal trace includes a second portion. The first portion is parallel to the second portion. The first signal trace and the second signal trace form a differential pair. The first signal trace is operable to conduct a positive portion of the signal, whereas the second signal trace is operable to conduct a negative portion of the signal.

Abstract: A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data.

Abstract: An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.

Abstract: An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.

Abstract: A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to a signal input and a tunable filter. The tunable filter comprises an input stage with a first pair of inductors arranged in a dipole configuration and a second tunable capacitor coupled in parallel to the first pair of inductors and an output stage inductively coupled to the input stage, the output stage includes a second pair of inductors also arranged in a dipole configuration and a third tunable capacitor coupled in parallel to the second pair of inductors. The inductors are realized using bond wire or any other high Q material. The first tunable capacitor, the second tunable capacitor, and the third tunable capacitor can be tuned using a master-slave tuning configuration to adjust the operating frequency of the amplifier and the tunable filter to enable frequency band compatibility with multiple communications protocols.

Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

Abstract: In a method and system for dicing a wafer (220), an ultraviolet (UV) laser (210) is aligned with a street (222) on the wafer (220). A thickness of the wafer (220) is at most 400 times a wavelength of the UV laser (210). When energized, the UV laser (210) generates an adjustable amount of energy in the form of a plurality of laser pulses (212) that are focused on the street (222). The amount of energy provided to the wafer (220) is adjustable in accordance to the thickness. The plurality of laser pulses (212) perform the dicing of the wafer (220) along the street (222) by ablating material from the wafer (220).

Abstract: In a method and system for relieving stress induced within a dielectric layer of a semiconductor device (100), areas in the dielectric layer (236, 238, 242) where the stress exceeds a threshold are identified. The areas, which are in parallel alignment with electrical interconnects such as conductive bumps (130), include a selected number of outer rows of the conductive bumps (130) having a high stress level. Within the identified areas where the stress exceeds the threshold, patterned zones (250) having an adjustable zone density are provided by adding reinforcing elements (240) to relieve the stress below the threshold.

Abstract: A plastic integrated circuit package often includes one or more integrated circuit elements that are sensitive to outside electromagnetic fields and also may generate electromagnetic fields that may interfere with other circuits outside of the package. The package herein has a top metal film to attenuate such electromagnetic fields, using a wire loop extending through the encapsulating compound to the metal film on top of encapsulating compound to provide electrical connection between top EMI film and end-and-ground junctions at grounds on die or on end-and-ground junctions at grounds on substrate.

Abstract: The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected percentage of the poly resistor exposed is formed on the poly resistor (110). A selected dopant is implanted (112), which modifies the resistivity of the poly resistor. The mask is removed (114) and a thermal activation process is performed (116) that diffuses the implanted dopant to a substantially uniform concentration throughout the polysilicon resistor.

Abstract: Disclosed are wirebonding methods wherein bondwires are positioned using dynamically determined variations in die placement. Preferred methods of the invention include steps for placing a die on the prepared substrate using selected ideal placement coordinates. Deviation of the actual die placement from the selected ideal placement coordinates is monitored, and one ore more critical bondwires are wirebonded between respective die pins and pins on the substrate. The monitored placement deviation is used to dynamically position the critical bondwires on the critical pins according to actual die placement. Disclosed embodiments include methods using lateral deviation monitoring and angular deviation monitoring to dynamically position bondwires.

Abstract: A semiconductor circuit comprising a semiconductor die and a package substrate. In one embodiment, a first plurality of conductive bumps serves as a portion of a conductive path between contacts on the semiconductor die and contacts on the package substrate. A second plurality of conductive bumps serves as a portion of a conductive path between other contacts on the die and contacts on the package substrate. Each of the bumps in the first plurality of conductive bumps is larger than each of the bumps in the second plurality of conductive bumps. In another embodiment, the average size of the first plurality of conductive bumps may be at least 20% larger (or greater) than the average size of the second plurality of bumps.

Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.

Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.