Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.

Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.