Abstract: A system may include a field programmable gate array (FPGA) based gateway comprising: a network interface configured to receive data packets containing proposed transactions, and validation logic circuitry configured to validate one or more headers or application-layer of the data packets in accordance with filter rules. The system may also include an FPGA based router comprising: a network interface configured to receive the data packets from the gateway, and parsing and lookup circuitry configured to compare the header field or application-layer field values in the data packets to those in a forwarding table. The system may also include an FPGA based matching engine comprising: a network interface configured to receive the data packets from the router, transaction validation circuitry configured to validate the proposed transactions based on information from state memory and policies, and matching algorithm circuitry configured to match pair of proposed transactions according to pre-determined criteria.

Abstract: The Multichannel Master Feeder Exchange Mechanism Apparatuses, Methods and Systems (“MMFEM”) transforms user share purchase, redemption request inputs via MMFEM components into fund share transaction records outputs. A processor-implemented non-transparent, master-feeder, master-feeder investment vehicle management, multichannel datastructure apparatus, comprising a processor and memory. The MMFEM memory having instructions to instantiate a multichannel asset vehicle configuration datapath and create a the multichannel vehicle data structure. The MMFEM may then determine a plurality of investment share data structures for the multichannel asset vehicle data structure and facilitate a transaction of investment shares data structures of the multichannel investment vehicle data structure based on the determined share price, wherein a master fund establishes a data feed for feeder funds to track.

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: A system may include a field programmable gate array (FPGA) based gateway comprising: a network interface configured to receive data packets containing proposed transactions, and validation logic circuitry configured to validate one or more headers or application-layer of the data packets in accordance with filter rules. The system may also include an FPGA based router comprising: a network interface configured to receive the data packets from the gateway, and parsing and lookup circuitry configured to compare the header field or application-layer field values in the data packets to those in a forwarding table. The system may also include an FPGA based matching engine comprising: a network interface configured to receive the data packets from the router, transaction validation circuitry configured to validate the proposed transactions based on information from state memory and policies, and matching algorithm circuitry configured to match pair of proposed transactions according to pre-determined criteria.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: Methods and systems for performing risk checks on electronic orders for securities. According to one embodiment, the method comprises performing risk checks on an electronic order for a security, the electronic order being issued from a client computer to an exchange computer via a network, wherein a risk check engine is logically interposed between the client computer and the exchange computer on the network. According to the illustrative method, at the risk check engine, the electronic order is received and parsed into one or more fields and data within the fields is identified at a network layer. The risk check engine performs one or more risk checks on the data using a processing element at the network layer. If the risk checks are passed, the risk check engine permits the electronic order to be transmitted to the exchange computer. If one or more of the risk checks are violated, the risk check engine rejects the order.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: An example embodiment may involve a network interface configured to transmit and receive frames. The embodiment may also involve a network protocol stack configured to: (i) perform encapsulation of outgoing messages into outgoing frames for transmission by way of the network interface, or (ii) perform decapsulation of incoming frames received by way of the network interface into incoming messages. The embodiment may also involve a parsing and validation module configured to: (i) receive representations of the incoming or the outgoing messages, and (ii) perform one or more validation checks on the representations, wherein the representations define transactions that are functionally equivalent to corresponding transactions that are defined by the messages, wherein the one or more validation checks are performed in parallel to performance of the encapsulation or decapsulation, and wherein a representation of a message failing the one or more validation checks causes the message to be discarded.

Abstract: A device may include a first interface and a second interface. The device may also include memory containing a set of rules and representations of pre-defined violations thereof. The device may also include digital logic programmed to: (i) receive, by way of the first interface, an Ethernet frame containing Ethernet header fields and an Ethernet payload, wherein the Ethernet payload contains a payload; (ii) extract data from the Ethernet header fields, wherein the data defines a transaction that is functionally equivalent to a further transaction that is defined by the payload; (iii) apply the set of rules to the transaction, wherein doing so involves comparing fields in the data to values and concluding that the transaction does not contain any pre-defined violations; and (iv) modify the Ethernet frame to contain content based on the payload, and transmit the Ethernet frame out the second interface.

Abstract: Methods and systems for performing risk checks on electronic orders for securities. According to one embodiment, the method comprises performing risk checks on an electronic order for a security, the electronic order being issued from a client computer to an exchange computer via a network, wherein a risk check engine is logically interposed between the client computer and the exchange computer on the network. According to the illustrative method, at the risk check engine, the electronic order is received and parsed into one or more fields and data within the fields is identified at a network layer. The risk check engine performs one or more risk checks on the data using a processing element at the network layer. If the risk checks are passed, the risk check engine permits the electronic order to be transmitted to the exchange computer. If one or more of the risk checks are violated, the risk check engine rejects the order.