Abstract: A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region.

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

Abstract: A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region.

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.