Abstract: Apparatus whereby data processing units exchange information with each other through a common memory without delay caused by limiting access to the memory to one data processing unit at a time.The invention includes a pair of random access memories (RAMS); a first logic circuit controlled by one of the data processing units (DPU) and the address signals from both DPUs; first and second sets of gates controlled by the first logic circuit to allow one DPU access to one RAM while the other DPU has access to the other RAM; and a second logic circuit (or "handshake" circuitry) to coordinate operation of the DPUs so that each DPU has read/write access to one or the other of the RAMs at all times. In operation, one DPU has access to one RAM while the other DPU has access to the other RAM. At the appropriate time, as determined by the handshake logic circuitry, the DPU access is switched between RAMs.