Patents by Inventor Gregory Haskins

Gregory Haskins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150371327
    Abstract: In an aspect of the subject matter, a system dynamically selects a communication fabric for use with a trading exchange platform. The system includes a gateway executing on the trading exchange platform, and a client side library executing on a customer device that interacts with application programs executing on the customer device. The gateway and customer device communicate during an initial session over an out-of-band network to select a communication fabric (e.g., InfiniBand, etc.) of one or more communications fabrics available to the customer device. The client side library communicates with the gateway to establish a transaction session over an in-band network utilizing the selected communication fabric. The library then allows the customer device to perform transactions with the gateway of trading exchange platform through the gateway during the transaction session and over the in-band network utilizing the selected fabric.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Moiz Kohari, Eric Baur, Gregory Haskins, Alex Tsariounov
  • Patent number: 7093072
    Abstract: Write transactions with large amounts of data using a typical cache may consume over half of the available backing store bandwidth because of the way traditional caching algorithms fill lines during a write-invoked eviction. Relaxing the traditional constraint of cache coherency improves write performance by eliminating unneeded cache line fills. This technique conserves backing store bandwidth during many write operations while having negligible impact on the cache's read performance.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 15, 2006
    Assignee: Enterasys Networks, Inc.
    Inventor: Gregory Haskins
  • Publication number: 20040168031
    Abstract: Write transactions with large amounts of data using a typical cache may consume over half of the available backing store bandwidth because of the way traditional caching algorithms fill lines during a write-invoked eviction. Relaxing the traditional constraint of cache coherency improves write performance by eliminating unneeded cache line fills. This technique conserves backing store bandwidth during many write operations while having negligible impact on the cache's read performance.
    Type: Application
    Filed: February 21, 2003
    Publication date: August 26, 2004
    Inventor: Gregory Haskins