Abstract: An improved network interface architecture for a packet switch provides a mechanism for handling voice and data packets. Bandwidth allocation can be changed because control and data memories are synchronized to one another. A hierarchical addressing technique is employed to enhance flexibility in handling packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. In an exemplary wireless TDMA packet network a control module (CM) sends a time stamp relative to the beginning of its frame in a synchronization packet allowing each of a plurality of user modules (UM) to maintain synchronization relative to the CM. The CM uses a plurality of directional antennas and transmits the synchronization packets over each antenna over a predetermined number of frames.