Abstract: An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.

Abstract: A capacitive sensor array may include a first sensor element of a first plurality of sensor elements, and a second sensor element. The second sensor element may include a plurality of subelements, where each of the plurality of subelements is connected to at least another of the plurality of subelements by one of a plurality of connecting traces. A width of each of the connecting traces may be less than a width of any of the plurality of subelements. Connecting traces in a subset of the plurality of connecting traces may be staggered about a central axis of the second sensor element.

Abstract: A capacitive sensor array may include a first sensor element of a first plurality of sensor elements, and a second sensor element. The second sensor element may include a plurality of subelements, where each of the plurality of subelements is connected to at least another of the plurality of subelements by one of a plurality of connecting traces. A width of each of the connecting traces may be less than a width of any of the plurality of subelements. Connecting traces in a subset of the plurality of connecting traces may be staggered about a central axis of the second sensor element.

Abstract: A protector for placement over subsea wellheads. A main body is cylindrical, with an inner diameter of sufficiant size to fit over a subsea wellhead. One end of the main body has a cap across it. A vent and a pump-through port, which permits pumping in of corrosion inhibitors, is in the cap. The open end of the main body has an outwardly flaring skirt to help guide the protector into place over the wellhead. The main body is formed from polyurethane via molding or other suitable methods.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: A method of testing, in parallel, a memory device including a plurality of memory cells organized into memory blocks, the memory device having a plurality of wired-OR pre-charged differential data line pairs, includes the steps of enabling a predetermined number of memory blocks at a time; writing to and reading as many bits as the predetermined number of enabled memory blocks in parallel; and detecting when both data lines of each of the wired-OR differential pairs are active at a same time, indicating that at least one bad memory cell exists within at least one of the predetermined number of enabled memory blocks.

Abstract: An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation.

Abstract: A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.

Abstract: A logic circuit implementing a logic NAND function with respect to a first input signal and a second input signal is described. First and second P-channel transistors are coupled in parallel to a power supply and an output node. Each of the first and second P-channel transistors receives the respective one of the first and second input signals. A first circuit branch has a first and a second N-channel transistor. The first N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the second N-channel transistor. The second N-channel transistor has a second end coupled to ground. The first N-channel transistor receives the first input signal and the second N-channel transistor receives the second input signal. A second circuit branch has a third and a fourth N-channel transistor. The third N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the fourth N-channel transistor.