Abstract: A delay apparatus of an embodiment is an apparatus for delaying a signal to a plurality of chain-based time-to-digital circuits (TDCs) and includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs. Each propagation path device is configured to delay a common start signal sent to each propagation path device by a selectable amount based on a delay selection signal received by the propagation path device, and to transmit the delayed start signal to the respective one of the TDCs.

Abstract: A delay apparatus of an embodiment is an apparatus for delaying a signal to a plurality of chain-based time-to-digital circuits (TDCs) and includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs. Each propagation path device is configured to delay a common start signal sent to each propagation path device by a selectable amount based on a delay selection signal received by the propagation path device, and to transmit the delayed start signal to the respective one of the TDCs.

Abstract: An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.

Abstract: An apparatus for delaying a plurality of chain-based time-to-digital circuits (TDCs). The apparatus includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs, each propagation path device delays a common start signal by a selectable amount based on a delay selection signal received by the propagation path device, and transmits the delayed start signal to the respective one of the TDCs.

Abstract: An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.

Abstract: A method and electronic device for outputting time values and energy of an analog input signal by dynamically determining a plurality of threshold values, comparing, using a plurality of comparator circuits, the plurality of threshold values against the analog input signal, outputting, using at least one time to digital conversion circuit connected to each of the plurality of comparator circuits, a plurality of time values, each time value output when the analog input signal meets or exceeds a threshold value of the threshold values, filtering the analog input signal, performing, using an analog-to-digital conversion circuit, analog-to-digital conversion of the filtered analog input signal to generate a digital signal, and calculating, in response to receiving a trigger signal, an energy of the digital signal.

Abstract: An apparatus for delaying a plurality of chain-based time-to-digital circuits (TDCs). The apparatus includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs, each propagation path device delays a common start signal by a selectable amount based on a delay selection signal received by the propagation path device, and transmits the delayed start signal to the respective one of the TDCs.

Abstract: An apparatus and method for inserting delay into a start signal of a metastable ring oscillator chain-based time-to-digital circuit (TDC). Included therein is a signal generating circuit that generates the start signal, a plurality of carry elements connected as a chain, each of the carry elements having an input to receive a stop signal, a delay chain circuit including one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs each provided in a respective one of the delay modules. The delay chain circuit generates an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay. The delay chain circuit additionally provides the selected amount of delay to the signal generating circuit, which incorporates the delay into the start signal.

Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.

Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.

Abstract: A method and electronic device for outputting time values and energy of an analog input signal by dynamically determining a plurality of threshold values, comparing, using a plurality of comparator circuits, the plurality of threshold values against the analog input signal, outputting, using at least one time to digital conversion circuit connected to each of the plurality of comparator circuits, a plurality of time values, each time value output when the analog input signal meets or exceeds a threshold value of the threshold values, filtering the analog input signal, performing, using an analog-to-digital conversion circuit, analog-to-digital conversion of the filtered analog input signal to generate a digital signal, and calculating, in response to receiving a trigger signal, an energy of the digital signal.

Abstract: A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.

Abstract: A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.

Abstract: A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.

Abstract: Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.

Abstract: Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.

Abstract: A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.

Abstract: A CRC redundancy calculation circuit is presented which is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.