Abstract: Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.

Abstract: Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.

Abstract: Power monitoring circuit 5000 monitors a positive power supply Vcc and a negative power supply Vee. If either one or both power supplies fall below predetermined respective threshold values, a master reset pulse (MR) is generated. When both power supplies are at their normal operating level, the logic circuit 5040 generates a signal that enables operation of the circuit.

Abstract: The A-to-D converter 300 has an output buffer 320 with fourteen drivers each the same as driver 4100. Driver 4100 includes bipolar pull up pull down transistors 4102, 4103. Those transistors are both coupled to an output. Pull up transistor 4102 is coupled to a first reference voltage VDD; pull down transistor 4103 is coupled to a second or ground reference potential. A base drive circuit comprising a series connection between a resistor and a transistor 4121 to provide additional current to saturate the pull down transistor 4103 and thereby lower the collector-to-emitter voltage drop of transistor 4103 when transistor 4103 is turned on.