Patents by Inventor Gregory John Mann

Gregory John Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure for hardware assisted bus state transition circuit using content addressable memories
    Patent number: 8347019
    Abstract: A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Serafino Bueti, Kenneth Joseph Goodnow, Todd Edwin Leonard, Gregory John Mann, Jason Michael Norman, Clarence Rosser Ogilvie, Peter Anthony Sandon, Charles S. Woodruff
  • DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT USING CONTENT ADDRESSABLE MEMORIES
    Publication number: 20080282015
    Abstract: A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Serafino Bueti, Kenneth Joseph Goodnow, Todd Edwin Leonard, Gregory John Mann, Jason Michael Norman, Clarence Rosser Ogilvie, Peter Anthony Sandon, Charles S. Woodruff
  • HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE MEMORIES.
    Publication number: 20080183941
    Abstract: A universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
    Type: Application
    Filed: January 26, 2007
    Publication date: July 31, 2008
    Applicant: International Business Machines Corporation
    Inventors: Serafino Bueti, Kenneth Joseph Goodnow, Todd Edwin Leonard, Gregory John Mann, Jason Michael Norman, Clarence Rosser Ogilvie, Peter Anthony Sandon, Charles S. Woodruff