Abstract: A electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

Abstract: An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

Abstract: A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized correspondence information. The wireless data retrieval device further includes an input/output device configured to transmit the standardized correspondence information to and receive said standardized correspondence information from a wireless channel.

Abstract: Embodiments of the present invention generally provide systems, methods and articles of manufacture for locating one component of callee information in response to receiving another associated component of the callee information. In a particular embodiment, a user inputs a network address (e.g., a telephone number) into a telephony device. The telephony device then operates to access a local directory in an effort to locate a callee name associated with a network address. If the callee name cannot be found in the local directory, a request for the callee name is transmitted to a remote directory.

Abstract: A redundancy circuit for a memory array and a method are provided for disabling non-redundant wordlines and for enabling redundant wordlines. A memory defect address is compared with a current address to be accessed. When there is a miscompare, the access to a non-redundant wordline is allowed to take place as normal. When the memory defect address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.

Abstract: A method and apparatus for providing correspondence information to a personal digital assistant (PDA) device. Examples of such correspondence information include business card information and calendar appointment information. The correspondence information is retrieved from a memory, translated into a format utilized by an operating system of the PDA device, and transmitted to the PDA device.

Abstract: A redundancy circuit for a memory array and a method are provided for disabling non-redundant wordlines and for enabling redundant wordlines. A memory defect address is compared with a current address to be accessed. When there is a miscompare, the access to a non-redundant wordline is allowed to take place as normal. When the memory defect address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.

Abstract: Silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined buried conduction layer to be connected to a SOI transistor source, and an intermediate conduction layer between the SOI transistor and the predefined buried conduction layer. A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silicide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An insulator is disposed between the second hole and the intermediate conduction layer.

Abstract: A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in multiple modes, including a scan mode for testing purposes.

Abstract: A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in a scan mode for testing purposes. In scan mode, one or more elements which normally function as master elements, function as slave elements. When operating in scan mode using this arrangement, the number of master elements in the pair of cells equals the number of slave elements, even though the number of master elements exceeds the number of slave elements during normal operation, permitting data to be successively scanned through all elements of the circuit.

Abstract: Methods and silicon-on-insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rail distribution. A SOI semiconductor structure includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined buried conduction layer to be connected to a SOI transistor source, and an intermediate conduction layer between the SOI transistor and the predefined buried conduction layer. A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silicide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An insulator is disposed between the second hole and the intermediate conduction layer.

Abstract: Embodiments of the present invention generally provide systems, methods and articles of manufacture for locating one component of callee information in response to receiving another associated component of the callee information. In a particular embodiment, a user inputs a network address (e.g., a telephone number) into a telephony device. The telephony device then operates to access a local directory in an effort to locate a callee name associated with a network address. If the callee name cannot be found in the local directory, a request for the callee name is transmitted to a remote directory.

Abstract: Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined burled conduction layer to be connected to a SOI transistor source, and an Intermediate conduction layer between the SOI transistor and the predefined buried conduction layer, A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silcide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An Insulator is disposed between the second hole and the intermediate conduction layer.

Abstract: A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized correspondence information. The wireless data retrieval device further includes an input/output device configured to transmit the standardized correspondence information to and receive said standardized correspondence information from a wireless channel.

Abstract: A method and apparatus for providing correspondence information to a personal digital assistant (PDA) device. Examples of such correspondence information include business card information and calendar appointment information. The correspondence information is retrieved from a memory, translated into a format utilized by an operating system of the PDA device, and transmitted to the PDA device.

Abstract: The present invention provides a method, apparatus and article of manufacture configured to allow off-line gaming. A client computer receives a gaming application and a token from a gaming provider server. The gaming application is configured to allow execution of one or more games on the client computer in the absence of a network connection with the gaming provider. The results of the games cause modification of the token. The token may then be redeemed for any residual value.

Abstract: A method and apparatus of eliminating the unwanted effects of parasitic bipolar discharge in dynamic logic circuits including silicon-on-insulator (SOI) field effect transistors (FET) by measuring setup time in a logic partition of a dynamic logic circuit having a precharging device and an output device. The method determines a first time delay of a clock signal from said logic partition to a control input of said precharging device and a second time delay of a logic signal from said logic partition to a control input of said output device. The method then determines a setup time according to said first and second time delays. The precharging device remains active during the setup time to prevent parasitic bipolar discharge.

Abstract: An improved latch circuit having a dynamically adjustable internal feedback level. The improved latch circuit includes a latch inverter and a feedback inverter cross-coupled with the latch inverter. A controllable supplemental feedback inverter is connected in parallel with the feedback inverter to provide a controllable level of feedback to the latch inverter. An independently selectable control signal enables or disables the controllable feedback inverter in conformity with a need for more or less feedback, such that the internal feedback level may provide optimal functionality and performance of the latch circuit.

Abstract: Methods and apparatus are provided for implementing adjustable logic threshold in dynamic circuits. The dynamic circuit includes an intermediate precharge node. An output logic stage is connected to the intermediate precharge node. A threshold adjustment circuit is connected to the output logic stage. The threshold adjustment circuit receives a selection input to adjust a threshold of the output logic stage. The threshold adjustment circuit is formed of a first transistor and a second transistor coupled in parallel with a pair of series connected transistors included in the output logic stage. One or both of the first transistor and second transistor are selectively activated to adjust the threshold of the output logic stage.

Abstract: A dynamic logic circuit is provided. The dynamic logic circuit includes at least one bitline. At least one repeater circuit is inserted into each bitline. The bitline repeater circuit includes an inverter and at least one transistor. The inverter is activated by the bitline starting to discharge and the activated inverter turns on the bitline repeater circuit transistor which discharges the bitline. The dynamic logic circuit including the bitline repeater circuit provides improved performance and decreased power consumption.