Abstract: The embodiments described herein are directed to systems and devices for electronically measuring the absolute position of one or more moving targets e.g., along the length of a metal beam using mutual capacitive sensing. The beam may be made of metal and may have a limited inset area to fit a position detection sensor device along its length. The moving targets may have no active elements and the position of multiple targets may be detected simultaneously along the beam. The systems and devices described herein do not utilize electronic position feedback and instead rely on an integrated ruler and minimize the total number of sensors required to support recalibration, thereby minimizing scan time (more sensors results in a linear increase in scan time).

Abstract: The embodiments described herein are directed to systems and devices for electronically measuring the absolute position of one or more moving targets e.g., along the length of a metal beam using mutual capacitive sensing. The beam may be made of metal and may have a limited inset area to fit a position detection sensor device along its length. The moving targets may have no active elements and the position of multiple targets may be detected simultaneously along the beam. The systems and devices described herein do not utilize electronic position feedback and instead rely on an integrated ruler and minimize the total number of sensors required to support recalibration, thereby minimizing scan time (more sensors results in a linear increase in scan time).

Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the TO pads.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or in an orthogonal fashion corresponding to the selected column. Thus, when a particular row is selected, a register operation may be carried out for each bit of the selected row to produce a parallel register output, such as by reading/writing each bit of the selected row to a parallel register. On the other hand, when a particular column is selected, a register operation may be carried out for each bit of the selected column, such as by reading/writing each bit of the selected column to an orthogonal register. The orthogonal register access allows for fast and efficient access to a particular bit in the set of parallel registers.