Patents by Inventor Gregory K. Deal

Gregory K. Deal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9141400
    Abstract: A guest disk may be setup through the assistance of a restore environment. A restore environment may be bundled with partitioning software, and the restore environment may be a small, lightweight Linux™ environment that is operating-system agnostic. The restore environment allows any operating system image file to be deployed on the guest disk. The guest disk may be created through the use of virtualization software and a guest operating system.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Unisys Corporation
    Inventors: Gregory K Deal, J. Troy Stepan, Maureen Connell
  • Publication number: 20140181493
    Abstract: Systems and methods are disclosed herein to a method of deploying a guest disk comprising: creating a plurality of virtual disks; partitioning each virtual disk into at least an OS partition and a data partition; launching virtualization software; booting the restore environment; downloading a OS partition image file and a data partition image file, wherein the OS partition image file and the data partition image file are smaller than a final system's OS and data partitions; expanding the OS partition image file onto the guest disk's OS partition to create an OS file system; expanding the data partition image file onto the guest disk's data partition to create a data file system; and resizing an OS file system and the data file system to access unused. portions of the OS and data partitions.
    Type: Application
    Filed: July 18, 2013
    Publication date: June 26, 2014
    Applicant: Unisys Corporation
    Inventors: Gregory K. Deal, J. Troy Stepan, Maureen Connell
  • Patent number: 6657504
    Abstract: A system of determining oscillation frequency of a ring oscillator formed on a chip. The system includes a ring oscillator formed on the chip for providing a ring clock signal having first periodic pulses, and a ring counter formed on the chip for providing a ring clock count value in response to the first periodic pulses. The system also includes a terminal for receiving a system clock signal having second periodic pulses, and a system counter formed on the chip for providing a system clock count value in response to the second periodic pulses. The oscillation frequency of the ring oscillator is determined based on the ring clock count value and the system clock count value.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: December 2, 2003
    Assignee: Unisys Corporation
    Inventors: Gregory K. Deal, David S. Milowicki, Chris E. Limson
  • Patent number: 6353915
    Abstract: A method for evaluating a system of interconnected electronic components is disclosed. According to the method, a library element model is generated for each electronic component in the system, in a format that can be input into an ASIC evaluation tool. A system netlist that represents the electronic components and the interconnections between them is generated, also in a format that can be input into an ASIC evaluation tool. The library element models and the system netlist are input into the ASIC evaluation tool, which is used to evaluate the system.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: March 5, 2002
    Assignee: Unisys Corporation
    Inventors: Gregory K. Deal, Mark W. Jennion, Oleg Rodionov
  • Patent number: 5590379
    Abstract: A two-way set associative cache memory system for a parallel-pipelined computer system uses separate queue structures to hold main memory fetch and store requests generated by the central processing unit (CPU). A memory access unit, coupled between the cache memory system and the CPU selects the next request to be processed by the main memory from between the requests at the heads of the fetch and store queues. The request at the head of the fetch queue is preferred over the request at the head of the store queue unless the memory partition to be used by the fetch request is still busy with a previous request while the partition to be used by the store request is idle. Data retrieved from the main memory replaces data in the cache according to an algorithm that prefers empty pages within a set to pages that contain data and prefers pages that do not have pending update requests scheduled to pages that do have pending update requests scheduled.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: December 31, 1996
    Assignee: Unisys Corporation
    Inventors: Joseph A. Hassler, Gregory K. Deal, Timothy A. Koss, Stephen F. Heil
  • Patent number: 5450564
    Abstract: A two-way set associative cache memory system for a parallel-pipelined computer system uses separate queue structures to hold main memory fetch and store requests generated by the central processing unit (CPU). A memory access unit, coupled between the cache memory system and the CPU selects the next request to be processed by the main memory from between the requests at the heads of the fetch and store queues. The request at the head of the fetch queue is preferred over the request at the head of the store queue unless the memory partition to be used by the fetch request is still busy with a previous request while the partition to be used by the store request is idle. Data retrieved from the main memory replaces data in the cache according to an algorithm that prefers empty pages within a set to pages that contain data and prefers pages that do not have pending update requests scheduled to pages that do have pending update requests scheduled.
    Type: Grant
    Filed: February 3, 1993
    Date of Patent: September 12, 1995
    Assignee: Unisys Corporation
    Inventors: Joseph A. Hassler, Gregory K. Deal, Timothy A. Koss, Stephen F. Heil
  • Patent number: 4704679
    Abstract: An address environment storage unit for a stack-oriented data processor for operating in data sets arranged as structured blocks, or nested pushdown stacks. The address environment storage employs a plurality of sets of display registers such that the current set of display registers does not have to be updated each time the processor moves to a different area of data in memory. The programmer only needs to provide a designation of a lexical level in a particular stack and the offset value from the base of the particular activation record in that stack for addition to obtain actual memory address. When the processor executes a procedure enter operator that calls for a new section of memory in which to operate, a display pointer is changed to point to the set of display registers provided for accessing that new area of memory.
    Type: Grant
    Filed: June 11, 1985
    Date of Patent: November 3, 1987
    Assignee: Burroughs Corporation
    Inventors: Joseph A. Hassler, Gregory K. Deal
  • Patent number: 4686691
    Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.
    Type: Grant
    Filed: December 4, 1984
    Date of Patent: August 11, 1987
    Assignee: Burroughs Corporation
    Inventors: Gregory K. Deal, Richard J. Manco