Patents by Inventor Gregory Kevern

Gregory Kevern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7332212
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: February 19, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Patent number: 7329446
    Abstract: The present invention provides a structure. The structure includes a stack of sheets. Successive sheets in each pair of successive sheets of the stack are coupled to each other by a removable adhesive. The removable adhesive is also disposed on top and bottom surfaces of the stack so as to respectively couple first and second layers to the cop and bottom surfaces of the stack.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: February 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Japp, Gregory A. Kevern, Francis S. Poch
  • Publication number: 20080032155
    Abstract: A structure. The structure includes a stack of two or more sheets. Successive sheets in each pair of successive sheets of the stack are adhesively coupled to each other by an adhesive layer consisting of a removable adhesive that is removable if heated to an elevated temperature at which the removable adhesive melts. The removable adhesive is also disposed on top and bottom surfaces of the stack. The removable adhesive consists of a liquid while adhesively coupling the successive sheets to each other. A first surface of a first layer coupled with the removable adhesive to a first surface of the stack. A first surface of a second layer is coupled with the removable adhesive to a second surface of the stack. The first and second layers are adapted to prevent burr formation in a hole subsequently drilled through the stack.
    Type: Application
    Filed: October 3, 2007
    Publication date: February 7, 2008
    Inventors: Robert Japp, Gregory Kevern, Francis Poch
  • Patent number: 7259333
    Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized voltage plane subassemblies; optionally an interposer located between each of the subassemblies, and wherein the subassemblies and interposer, if present, are bonded together with a cured dielectric coating. The interposer comprises dielectric layers disposed about an internal electrically conductive layer.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 21, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert Japp, Gregory Kevern, William Rudik
  • Patent number: 7063762
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: June 20, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Publication number: 20060029781
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Application
    Filed: October 5, 2005
    Publication date: February 9, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Publication number: 20050048408
    Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized voltage plane subassemblies; optionally an interposer located between each of the subassemblies, and wherein the subassemblies and interposer, if present, are bonded together with a cured dielectric coating. The interposer comprises dielectric layers disposed about an internal electrically conductive layer.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Japp, Gregory Kevern, William Rudik
  • Publication number: 20050039840
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Application
    Filed: August 20, 2003
    Publication date: February 24, 2005
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Patent number: 6834426
    Abstract: A method for fabricating a laminate circuit structure is provided. The method comprises: providing at least two modularized circuitized voltage plane subassemblies wherein each of the subassemblies comprise at least two signal planes having an external and internal surface disposed about an internal voltage plane; providing a dielectric material between the signal and voltage planes; and providing dielectric on each external surface of each signal plane; and providing a non-cured or partially cured curable dielectric composition between the subassemblies wherein the dielectric composition comprises, dielectric material that is of the same material as the dielectric material used in said subassemblies, aligning the subassemblies, and then laminating to cause bonding of the subassemblies.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: December 28, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Japp, Gregory A. Kevern, William J. Rudik
  • Publication number: 20040086741
    Abstract: The present invention provides a method of temporarily adhering a stack of sheets together to facilitate drilling a hole through the stack of sheets. The method includes using a temporary adhesive that prevents burring while drilling a hole through the stack.
    Type: Application
    Filed: October 23, 2003
    Publication date: May 6, 2004
    Inventors: Robert M. Japp, Gregory A. Kevern, Francis S. Poch
  • Patent number: 6669805
    Abstract: The present invention provides a method of temporarily adhering a stack of sheets together to facilitate drilling a hole through the stack of sheets. The method includes using a temporary adhesive that prevents burring while drilling a hole through the stack.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Japp, Gregory A. Kevern, Francis S. Poch
  • Publication number: 20030022013
    Abstract: The present invention provides a method of temporarily adhering a stack of sheets together to facilitate drilling a hole through the stack of sheets. The method includes using a temporary adhesive that prevents burring while drilling a hole through the stack.
    Type: Application
    Filed: February 16, 2001
    Publication date: January 30, 2003
    Applicant: International Business Machines Corporation
    Inventors: Robert M. Japp, Gregory A. Kevern, Francis S. Poch
  • Patent number: 6395998
    Abstract: An electronic package and method of making the electronic package is provided. An opening in a thermally conductive member of the electronic package is formed to substantially prevent adhesive which can bleed from under a substrate mounted and secured on the thermally conductive member from contacting a portion of the thermally conductive member upon which an electrical element will be mounted.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Donald S. Farquhar, Gregory A. Kevern, Michael J. Klodowski