Patents by Inventor Gregory Kevern

Gregory Kevern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7332212
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: February 19, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Publication number: 20080032155
    Abstract: A structure. The structure includes a stack of two or more sheets. Successive sheets in each pair of successive sheets of the stack are adhesively coupled to each other by an adhesive layer consisting of a removable adhesive that is removable if heated to an elevated temperature at which the removable adhesive melts. The removable adhesive is also disposed on top and bottom surfaces of the stack. The removable adhesive consists of a liquid while adhesively coupling the successive sheets to each other. A first surface of a first layer coupled with the removable adhesive to a first surface of the stack. A first surface of a second layer is coupled with the removable adhesive to a second surface of the stack. The first and second layers are adapted to prevent burr formation in a hole subsequently drilled through the stack.
    Type: Application
    Filed: October 3, 2007
    Publication date: February 7, 2008
    Inventors: Robert Japp, Gregory Kevern, Francis Poch
  • Patent number: 7259333
    Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized voltage plane subassemblies; optionally an interposer located between each of the subassemblies, and wherein the subassemblies and interposer, if present, are bonded together with a cured dielectric coating. The interposer comprises dielectric layers disposed about an internal electrically conductive layer.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 21, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert Japp, Gregory Kevern, William Rudik
  • Patent number: 7063762
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: June 20, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Publication number: 20060029781
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Application
    Filed: October 5, 2005
    Publication date: February 9, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Publication number: 20050048408
    Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized voltage plane subassemblies; optionally an interposer located between each of the subassemblies, and wherein the subassemblies and interposer, if present, are bonded together with a cured dielectric coating. The interposer comprises dielectric layers disposed about an internal electrically conductive layer.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Japp, Gregory Kevern, William Rudik
  • Publication number: 20050039840
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Application
    Filed: August 20, 2003
    Publication date: February 24, 2005
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent