Abstract: A parallel processor array with a two-dimensional crossbar switch architecture. Individual processing elements are configured as clusters of processors, wherein the individual processing elements within each cluster are interconnected by a two dimensional cluster network of crossbar switch elements. The clusters are interconnected via a two dimensional array network of crossbar switch elements, supporting high-bandwidth inter-processor data shuffles that characterize parallel implementations of sensor processing problems. Input data is supplied directly into the array network of crossbar switch elements, which allows an optimal initial partitioning of the data set among the processing elements. The array architecture supports a virtual array sizing, where the processor array can be treated as a variable sized array with dimensions that are software controllable, selectable to match system characteristics.