Patents by Inventor Gregory L. Cowan

Gregory L. Cowan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system for utilizing the semiconductor integrated circuit
    Patent number: 6665827
    Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: December 16, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Roland Ochoa, Gregory L. Cowan, Kim M. Pierce
  • Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
    Publication number: 20030110428
    Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
    Type: Application
    Filed: January 14, 2003
    Publication date: June 12, 2003
    Inventors: Roland Ochoa, Gregory L. Cowan, Kim M. Pierce
  • Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
    Patent number: 6546512
    Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: April 8, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Roland Ochoa, Gregory L. Cowan, Kim M. Pierce
  • Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
    Patent number: 6314538
    Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: November 6, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Roland Ochoa, Gregory L. Cowan, Kim M. Pierce
  • Output data compression scheme for use in testing IC memories
    Patent number: 6016561
    Abstract: A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: January 18, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Fariborz F. Roohparvar, Allahyar Vahidi Mowlavi, Mark A. Hawes, Gregory L. Cowan
  • Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
    Patent number: 5864565
    Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: January 26, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Roland Ochoa, Gregory L. Cowan, Kim M. Pierce
  • Output data compression scheme for use in testing IC memories
    Patent number: 5787097
    Abstract: A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: July 28, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Fariborz F. Roohparvar, Allahyar Vahidi Mowlavi, Mark A. Hawes, Gregory L. Cowan