Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for classifying data objects. One of the methods includes obtaining data that associates each term in a vocabulary of terms with a respective high-dimensional representation of the term; obtaining classification data for a data object, wherein the classification data includes a respective score for each of a plurality of categories, and wherein each of the categories is associated with a respective category label; computing an aggregate high-dimensional representation for the data object from high-dimensional representations for the category labels associated with the categories and the respective scores; identifying a first term in the vocabulary of terms having a high-dimensional representation that is closest to the aggregate high-dimensional representation; and selecting the first term as a category label for the data object.

Abstract: The invention is directed to a system for securing an integrated circuit chip used in an electronic device by utilizing a circuit or other entity to produce physically unclonable functions (PUF) circuit to generate encryption keys, such as an RSA public or private key. A PUF circuit, according to its name and configuration, performs functions that are substantially difficult to be duplicated or cloned. This allows the invention to provide a unique and extremely secure system for authentication. In operation, the stored parameters can be used to more efficiently and quickly authenticate the device without the need to run the usual more burdensome encryption key generation processes without compromising the level of security in the device. Such a system can be used to substantially eliminate the time to produce encryption keys when a user needs to authenticate the device at power up or other access point.

Abstract: A system for securing an integrated circuit chip used for biometric sensors, or other electronic devices, by utilizing a physically unclonable function (PUF) circuit. These PUF functions are in turn used to generate security words and keys, such as an RSA public or private key. Such a system can be used to protect biometric security sensors and IC chips, such as fingerprint sensors and sensor driver chips, from attack or spoofing. The system may also be used in an efficient method to produce unique device set-up or power-up authentication security keys. These keys can be generated on a low frequency basis, and then frequently reused for later security verification purposes. In operation, the stored keys can be used to efficiently authenticate the device without the need to frequently run burdensome security key generation processes each time, while maintaining good device security.

Abstract: The invention is directed to a system for securing an integrated circuit chip used in an electronic device by utilizing a circuit or other entity to produce physically unclonable functions (PUF) to generate a security word, such as an RSA public or private key. A PUF, according to its name and configuration, performs functions that are substantially difficult to be duplicated or cloned. This allows the invention to provide a unique and extremely secure system for authentication. In operation, the stored parameters can be used to more efficiently and quickly authenticate the device without the need to run the burdensome security key generation processes without compromising the level of security in the device. Such a system can be used to substantially eliminate the time to produce security keys when a user needs to authenticate the device at power up or other access point.

Abstract: A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer includes a PLL core and a feedback frequency divider. The PLL core receives an F(in) signal and generates a plurality of multiphase output signals having an F2 frequency, where F2=(in)(P+?p). The feedback frequency divider receives the plurality of multiphase output signals and generates a feedback signal having a frequency of F2/(P+?p), where P is an integer and ?p is a fractional value less than one.

Abstract: A PLL frequency synthesizer tunable in small step sizes that comprises: 1) a first PLL circuit comprising: i) a first feedforward frequency divider that receives an F(in) frequency and generates an F1 frequency, where F1=F(in)/P, ii) a first PLL core that receives the F1 frequency and generates an F2 frequency, where F2=(P+&Dgr;p)F1, and iii) a first feedback frequency divider that receives the F2 frequency and generates a first feedback signal having frequency F2/(P+&Dgr;p); and 2) a second PLL circuit comprising: i) a second feedforward frequency divider that receives the F2 frequency and generates an F3 frequency, where F3=F2/(N+&Dgr;n), ii) a second PLL core that receives the F3 frequency and generates an F(out) frequency, where F(out)=(N)F3, and iii) a second feedback frequency divider that receives the F(out) frequency and generates a second feedback signal having frequency F(out)/(N).

Abstract: A character line address counter clock signal generator for generating a character line address counter clock signal for an on screen display (OSD) circuit used to selectively display a character image within an on screen display contained within a displayed screen image. The character image displayed within the OSD is maintained at a substantially constant image height regardless of the number of image lines contained within the overall displayed screen image. The character image lines for a base character image are displayed in accordance with a predetermined repetition sequence without requiring phase lock loop to generate a reduced character line address clock or requiring arithmetic computation to calculate each character line address.

Abstract: A broadcast digital sound processing system includes an ISA (Industry Standard Architecture) bus compatible personal computer with a hard disk drove and a sound processor board installed in an expansion slot of the computer. The board includes a stereo input, analog to digital converter (ADC) and a stereo set of digital to analog converters (DAC's) interfaced to a digital signal processor (DSP) chip. A stereophonic audio signal is converted to digital data by the ADC and communicated to the computer by the DSP chip through a two port record first-in/first-out (FIFO) buffer for storage on the disk. A program is played back by communicating a program data file through a two port playback FIFO buffer to the DSP and from there to the DAC's for reconstruction to a stereo set of analog signals. The reconstructed audio signals may then be used as a modulating signal for radio broadcasting.

Abstract: A broadcast digital sound processing system includes an ISA (Industry Standard Architecture) bus compatible personal computer with a hard disk drive and a sound processor board installed in an expansion slot of the computer. The board includes a stereo input, analog to digital converter (ADC) and a stereo set of digital to analog converters (DAC's) interfaced to a digital signal processor (DSP) chip. A stereophonic audio signal is converted to digital data by the ADC and communicated to the computer by the DSP chip through a two port record first-in/first-out (FIFO) buffer for storage on the disk. A program is played back by communicating a program data file through a two port playback FIFO buffer to the DSP and from thee to the DAC's for reconstruction to a stereo set of analog signals. The reconstructed audio signals may then be used as a modulating signal for radio broadcasting.