Abstract: An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

Abstract: A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Abstract: A method of fabricating a MESFET is comprised of providing a semiconductor material having a channel region formed therein, forming a gate on the semiconductor material over the channel region, forming a spacer adjacent a first portion of the gate disposed on the semiconductor material, and forming a hard mask disposed on a second portion of the gate and on a portion of the semiconductor material.

Abstract: The present invention provides a III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Abstract: There are disclosed liquid crystal displays each having at least one pixel element formed on an insulative substrate including at least two conductive electrodes and liquid crystal display material disposed between the electrodes. The pixel elements further include at least a pair of isolation devices formed from a deposited semiconductor material which facilitates selective excitation of of the pixel elements and applied potential reversal across the electrodes during alternate display frames. The isolation devices can include a plurality of series connected diodes. The isolation devices can be formed as diode rings. A method of making the displays is also disclosed.

Abstract: There are disclosed liquid crystal displays each having at least one pixel element formed on an insulative substrate including at least two conductive electrodes and liquid crystal display material disposed between the electrodes. The pixel elements further include at least a pair of isolation devices formed from a deposited semiconductor material which facilitates selective excitation of the pixel elements and applied potential reversal across the electrodes during alternate display frames. The isolation devices can include a plurality of series connected diodes. The isolation devices can be formed as diode rings. A method of making the displays is also disclosed.

Abstract: A quick testable subassembly with redundant isolation devices usable in a liquid crystal display has a pair of coplanar spaced apart electrode segments connected to one or more-isolation devices. Address lines are connected to the isolation devices or the electrodes. The isolation devices and electrical connections to the electrode segments can be quickly tested prior to assembly of a complete display. Redundant isolation devices are formed on the subassembly and inoperative isolation devices can be replaced by associated redundant isolation devices. A method of quickly testing the subassembly and of replacing inoperative isolation devices, and several alternate quickly testable subassembly geometries are also disclosed. A self-selecting redundant geometry and method are also disclosed.

Abstract: A new and improved thin film field effect transistor and method provides such a transistor having increased operating frequencies and higher output currents. The transistor includes a gate electrode having a non-coplanar surface with respect to the substrate and a deposited semiconductor material overlying the gate electrode to form a current conductor channel between a source and drain. The length of the current conduction channel is determined by the thickness of the gate electrode which can be accurately controlled. As a result, short channel lengths are possible without high precision photolithography for high output currents and fast operating speeds. Further, a gate insulator is disposed between the gate and the deposited semiconductor. The gate insulator, which can be a gate oxide, can be annealed prior to the deposition of the deposited semiconductor to provide enhanced field effect mobilities. This further increases the transistor output currents and operating speeds.

Abstract: Light influencing subassemblies and displays each having a structure in which all of the pixel electronic circuitry, including isolation devices where utilized, are located at one electrode side of each pixel electrode combination. The structure includes the subdivision of one pixel electrode into at least two spaced apart side-by-side electrode segments opposite a common electrode. The displays include light influencing material disposed between the segmented and common electrodes. The electrode segments further can include at least one isolation device coupled to at least one of the segments which facilitates selective excitation of the pixel elements and applied potential reversal across the electrodes during alternate display frames. The displays have an increased manufacturing yield, reduced capacitance and increased isolation. Also disclosed is a method of making the subassemblies and displays.

Abstract: A new and improved thin film field effect transistor has increased operating current and speed. The transistor includes a drain, an insulator, and a source formed in layers and vertically arranged with respect to a substrate and each other. The drain, however, and source layers form a plurality of non-coplanar surfaces with respect to the substrate. The device further includes a deposited semiconductor material overlying the non-coplanar surfaces to form a plurality of current conduction channels between the drain and source. A gate insulator overlies the semiconductor material, and a gate electrode overlies the gate insulator. The devices can also include carrier injection structure including a doped semiconductor material electrically coupled to the drain, the source, and the deposited semiconductor material for increasing the injection of current conduction carriers in the current conduction channels.