Abstract: A high speed gain stage including regenerative feedback that forces one output high and one output low providing a two-state output. A differential pair of input transistors of a first conductivity type have respective current terminals coupled between a source node and first and second output nodes and have respective control terminals that receive the analog input voltages. A current source provides source current to the source node. The gain stage includes a differential pair of bias transistors of a second conductivity type having respective current terminals coupled between the first and second output nodes and a reference voltage and having respective control terminals coupled to a bias node. A pair of current-driven transistors of the second conductivity type are cross-coupled at the outputs and to a common node to provide the regenerative feedback. Another transistor is coupled between the common node and the reference voltage to increase switching speed.

Abstract: A low voltage to high voltage level translator that is independent of the high supply voltage. The translator includes first and second transistors with current terminals coupled to a first supply voltage and control terminals that are cross-coupled to one of first and second output nodes. The translator includes first and second input stages each having a first current terminal coupled to a second supply voltage, having a second current terminal coupled to one of the first and second output nodes, and having a control terminal coupled to one of first and second input nodes. The translator further includes first and second resistors, each having a first terminal coupled to the second current terminal of one of the first and second transistors and a second terminal coupled to one of the first and second output nodes. The added resistors enable wider voltage translation and avoid conventional configuration issues.

Abstract: A current to current charge pump including two flying capacitors, a capacitor driver, two rectifying inverters, a bypass capacitor coupled between an input node and a control node, a current control transistor circuit coupled between the control node and a reference node, and an output circuit coupled between upper and lower nodes. One of the upper and lower nodes is held at a constant voltage level. A storage capacitor is coupled between the upper and lower nodes. The capacitor driver drives each of the flying capacitors to opposite states between the control and input nodes using a clock signal. The rectifying inverters are cross-coupled between the flying capacitors, and have supply terminals coupled between the upper and lower nodes. The current control transistor circuit develops an input current at the control node based on a reference current. The output transistor circuit develops an output current that follows the input current.

Abstract: A precision, high voltage, low power differential input stage including static and dynamic gate protection is disclosed herein. The differential input stage incorporates the performance of low voltage transistors with the high voltage capability of high voltage transistors. The transistors may be MOSFETs or the like. In addition, gate protection is provided to protect against large DC voltages and AC voltage transitions. The differential input stage includes a pair of input circuits, such as positive and negative input circuits, each including a cascode combination of low and high voltage transistors. In each cascode stage, the low voltage transistor is fabricated with a gate threshold voltage that is as high or higher than that of the high voltage transistors. The low voltage, high threshold transistors in the cascode stages may be configured to match each other. Resistors and capacitors may be provided to protect against excessive input current and voltage.

Abstract: A precision, high voltage, low power differential input stage including static and dynamic gate protection is disclosed herein. The differential input stage incorporates the performance of low voltage transistors with the high voltage capability of high voltage transistors. The transistors may be MOSFETs or the like. In addition, gate protection is provided to protect against large DC voltages and AC voltage transitions. The differential input stage includes a pair of input circuits, such as positive and negative input circuits, each including a cascode combination of low and high voltage transistors. In each cascode stage, the low voltage transistor is fabricated with a gate threshold voltage that is as high or higher than that of the high voltage transistors. The low voltage, high threshold transistors in the cascode stages may be configured to match each other. Resistors and capacitors may be provided to protect against excessive input current and voltage.

Abstract: A differential input stage including two input branches each with a pair of transistors. A bias circuit supplies a separate bias current to each of the input branches. A first transistor of each branch has a first current terminal coupled to a source node receiving a bias current, a second current terminal coupled to an output node, and a control terminal coupled to an input node. A second transistor of each branch has a first current terminal coupled to the corresponding source node, a control terminal coupled to the corresponding input node, and a second current terminal coupled to an intermediate node. The second transistors operate as a current path in higher differential voltage conditions to keep the first transistor active to avoid violating the maximum gate-source voltage.

Abstract: A switched capacitor voltage reference including a single bias current source, three capacitors, diode devices, an amplifier and switching circuits for developing a temperature independent reference voltage. A single current source avoids having to match multiple current sources. A first capacitor and at least one diode device set a voltage having a negative temperature coefficient. A second capacitor and each of the diode devices set a voltage having a positive temperature coefficient. A third capacitor allows adjustable gain to enable a wide voltage range including a low voltage such as less than one volt. The switching circuits switch between multiple modes for developing and then combining the different temperature coefficient voltages. The topology allows a simple amplifier to be used. The topology is inherently accurate and does not require device trimming. An averaging method may be used to compensate for any mismatch between the diode devices.

Abstract: A switched capacitor voltage reference including a single bias current source, three capacitors, diode devices, an amplifier and switching circuits for developing a temperature independent reference voltage. A single current source avoids having to match multiple current sources. A first capacitor and at least one diode device set a voltage having a negative temperature coefficient. A second capacitor and each of the diode devices set a voltage having a positive temperature coefficient. A third capacitor allows adjustable gain to enable a wide voltage range including a low voltage such as less than one volt. The switching circuits switch between multiple modes for developing and then combining the different temperature coefficient voltages. The topology allows a simple amplifier to be used. The topology is inherently accurate and does not require device trimming. An averaging method may be used to compensate for any mismatch between the diode devices.

Abstract: A fully differential amplifier with automatic offset voltage zeroing including first and second dynamically switched current mirrors and an output circuit. Each current mirror toggles operation between an autozeroing phase in which it mirrors a first current level indicative of a level of a first input terminal to provide a mirrored current, and an output phase in which it applies a difference current to a common output node. The difference current is a difference between the mirrored current and a second current level indicative of a level of a second input terminal. The first and second dynamically switched current mirrors operate out of phase with respect to each other during respective periods of each cycle of a clock signal. The output circuit develops first and second output signals on first and second output terminals at first and second polarities, respectively, based on a level of the common output node.

Abstract: A fully differential amplifier with automatic offset voltage zeroing including first and second dynamically switched current mirrors and an output circuit. Each dynamically switched current mirror toggles operation between an autozeroing phase in which it mirrors a first current level indicative of a level of a first input terminal to provide a mirrored current, and an output phase in which it applies a difference current to a common output node. The difference current is a difference between the mirrored current and a second current level indicative of a level of a second input terminal. The first and second dynamically switched current mirrors operate out of phase with respect to each other during respective periods of each cycle of a clock signal. The output circuit develops first and second output signals on first and second output terminals at first and second polarities, respectively, based on a level of the common output node.

Abstract: A circuit for controllably coupling an input to an output. The circuit includes: (1) a pass transistor having an emitter, a collector and a base, the emitter being coupled to the input, the collector being coupled to the output; (2) a second transistor coupled to the pass transistor, and biased to operate with a collector-to-base voltage approximately equal to zero; and (3) a control circuit coupled to the input, the output and the base of the pass transistor, the control circuit controllably turning the pass transistor on. When the pass transistor is turned on, the control circuit maintains in the pass transistor a collector current approximately equal to a predetermined scale factor times the collector current of the second transistor. The predetermined scale factor ensures that the pass transistor operates at the edge of a saturation region when the pass transistor is turned on.

Abstract: Disclosed is an operational amplifier having a positive input terminal, a negative input terminal, an output terminal, a positive power supply input and a negative power supply input. The operational amplifier includes a transistor input pair being coupled to the positive input terminal and the negative input terminal. A first charge pump being coupled to positive supply circuitry contained within the operational amplifier. The first charge pump being configured to operate the positive supply circuitry contained within the operational amplifier at an enhanced positive power supply. The operational amplifier further includes a second charge pump being coupled to negative supply circuitry contained within the operational amplifier. The second charge pump being configured to operate the negative circuitry contained within the operational amplifier at an enhanced negative power supply. Accordingly, the transistor output pair provides an essentially full rail-to-rail output.

Abstract: Dual interleaved DC to DC switching circuits realizable in an integrated circuit form, capable of monitoring individual inductor current using only one current sense resistor and providing automatic duty cycle adjustment to keep the inductor currents in the interleaved DC to DC switching circuits balanced. The preferred embodiment includes a gain error amplifier, an integral error amplifier, and a differentiator error amplifier and circuits for controlling the nominal duty cycle, with the gain error amplifier, integral error amplifier and differentiator error amplifier being adjustable independently by external components. The circuit further includes a high speed load regulation circuit that momentarily overrides the control circuitry to take over control of the interleaved converters during sudden load changes, such control also being programmable.

Abstract: A DC--DC converter capable of both step-up and step-down operations includes a synchronous rectifier coupled between a rectifier connection and an output node, an inductor coupled between an input node and the rectifier connection, a rectifier control circuit for controlling the synchronous rectifier, the rectifier control circuit coupled to the input node, to the synchronous rectifier, to the rectifier connection and to the output node, and a switch coupled between the rectifier connection and ground. After closing the switch to build up energy in the inductor, the synchronous rectifier turns on simultaneously with the opening of the switch when the voltage of the rectifier connection is greater than the voltage of the output node and the voltage of the input node. The synchronous rectifier turns off when a current through the inductor becomes zero or when the switch closes again.

Abstract: Methods and apparatus for improving the temperature drift of references by providing temperature compensation trimmable after packaging of the integrated circuit. In accordance with the method, first, second and third trim parameters are generated and trimmed at wafer sort so that the first parameter is substantially independent of temperature, and at a nominal temperature, the second and third parameters are zero, with the second being proportional to the temperature rise above nominal and the third being proportional to temperature decrease below nominal.

Abstract: A self-contained, bi-polar high-side current sense amplifier which detects the magnitude and polarity of current flowing from one device to another, is disclosed. The amplifier has a symmetric architecture having two inputs and two outputs. One output is active for positive input signals corresponding to current flow in one direction, and the other output is active for negative input signals corresponding to current flow in an opposite direction. A symmetric current mirror in the amplifier provides the OR'ing function required to provide only one output at a time. The amplifier also utilizes aluminum sense and gain resistors, which allows cancellation of resistor temperature coefficients.

Abstract: A transconductance amplifier intended for high frequency, precision amplification. The amplifier has a unique architecture that sets gain by the ratio of two impedances. Unlike conventional amplifiers, the amplifier does not use external feedback. This makes the amplifier unusually stable since one needn't worry about phase shift due either to the amplifier or a feedback network. Consequently, the amplifier can be used in some rather unusual circuit applications, some of which would be impossible with conventional (feedback) amplifiers. Various embodiments are disclosed.

Abstract: A CMOS output amplifier having a symmetrical output and a high ratio of output drive current to quiescent current. The amplifier uses first and second complementary devices connected in series between power supply connections with the output taken from the connection between the two devices. The input to the output stage is provided to the gate of the first device and to the gate of a third device of the same type as the second device, the source of the third device being maintained at a voltage which is independent of the input signal. The current through the third device is mirrored to the second device in a ratio of 1:N. Current sourcing and sinking capabilities of the output stage are an order of magnitude larger than the quiescent current requirements.

Abstract: A bandgap voltage reference of a unique design is disclosed. The reference utilizes a pair of transistors operating at different current densities to provide a current component through a resistor at the .DELTA.V.sub.BE of the two transistors. A second current component through the resistor is provided through another resistor connected to the common emitter connection of another pair of transistors, the collectors of the last named pair of transistors each being connected to one input of a operational amplifier, the output of which is the output of the circuit.

Abstract: Dual interleaved DC to DC switching circuits realizable in an integrated circuit form, capable of monitoring individual inductor current using only one current sense resistor and providing automatic duty cycle adjustment to keep the inductor currents in the interleaved DC to DC switching circuits balanced. The preferred embodiment includes a gain error amplifier, an integral error amplifier, and a differentiator error amplifier and circuits for controlling the nominal duty cycle, with the gain error amplifier, integral error amplifier and differentiator error amplifier being adjustable independently by external components. The circuit further includes a high speed load regulation circuit that momentarily overrides the control circuitry to take over control of the interleaved converters during sudden load changes, such control also being programmable.