Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract: A method leverages knowledge of the actual or ideal bit sequence to improve the performance of any sequence detector. This improved performance results by constraining the sequence detector when the sequence detector has knowledge of known patterns within the sample sequence. Embodiments may control or limit the effects of ISI on a readback signal in order to allow higher storage within physical media such as that of a HDD. This method involves reading an analog waveform from the physical media. The phase of this analog waveform is determined and it is sampled at regular intervals using a timing recovery scheme. This sample sequence is equalized (filtered) and sent to a sequence detector which will compare the received sequence to all possible transmitted sequences, generating a path through a trellis that represents the estimated sequence. That trellis path may pass through known states at certain times. This knowledge makes it possible to remove some of the paths under consideration.

Abstract: Error correction coding using soft information and interleaving. A symbol interleaved ECC signal (which can be a symbol interleaved multi-level ECC signal) initially undergoes detection (e.g., such as using SOVA detection) to generate soft information. A decoder uses the soft information to generate estimates of at least one symbol (or at least one bit) of the symbol interleaved multi-level ECC signal. Initially, each of the interleaves of the symbol interleaved multi-level ECC signal undergo decoding to determine whether or not any of the interleaves has correctable errors. If not, then a receiving device can request re-transmission of the symbol interleaved multi-level ECC signal from a transmitting device (or a re-read from media of a hard disk drive (HDD)). Interleaves having uncorrectable errors are associated with interleaves having correctable errors. Uncorrectable errors can be corrected via the use of erasure pointers or bit-flipping, among other means.

Abstract: A communications channel is provided, which includes a receive path having an iterative decoder and an ECC decoder. The iterative decoder has a soft channel detector with a soft output. The ECC decoder is coupled to decode bits produced from soft information received from the soft output and operates on the bits in a bit order that is the same as that on the soft output.

Abstract: A method or apparatus that can form and test a data block variant by flipping a selected potentially bad bit that is consecutive with 1 or 2 sequences of several potentially good bits of a received block. The variant correctability test is optionally repeated several times before receiving another data block, in the event of ECC failures, each repetition using a different block variant.

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract: A method leverages knowledge of the actual or ideal bit sequence to improve the performance of any sequence detector. This improved performance results by constraining the sequence detector when the sequence detector has knowledge of known patterns within the sample sequence. Embodiments may control or limit the effects of ISI on a readback signal in order to allow higher storage within physical media such as that of a HDD. This method involves reading an analog waveform from the physical media. The phase of this analog waveform is determined and it is sampled at regular intervals using a timing recovery scheme. This sample sequence is equalized (filtered) and sent to a sequence detector which will compare the received sequence to all possible transmitted sequences, generating a path through a trellis that represents the estimated sequence. That trellis path may pass through known states at certain times. This knowledge makes it possible to remove some of the paths under consideration.

Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract: A technique to sample a signal from a disk by using frequency and phase offset adjustment in a phase locked loop (PLL) timing recovery loop to sample read data from the disk, prior to a disk clocked clocking acquires a lock. Subsequently, sampling a signal from a disk by using only phase offset adjustment in the PLL timing recovery loop to sample read data from the disk after the disk clocked clocking acquires the lock. The sampled data is then error corrected by applying an error correction code (ECC).

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract: A signal processing system includes a receiver for receiving an analog signal. The system also includes an analog-to-digital converter (ADC) coupled to the receiver. At each of a series of time intervals, the ADC outputs sequential digital codes. Each digital code corresponds to a sampled analog value of the received analog signal at each sample interval. The system further includes a memory in which the sequential digital codes may be stored, and a processing circuit for converting the digital codes into a series of binary data bits. The conversion may be performed in a different sequence than the sequence in which the digital codes are stored in the memory.

Abstract: A method and apparatus for communicating data is provided. The data is encoded in accordance with a run length limited (RLL) code. A seed is appended to the RLL encoded data. The seed can be used to alter the error correction code (ECC) parity to meet an RLL constraint.

Abstract: An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.