Patents by Inventor Gregory L. Timp

Gregory L. Timp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a composite gate dielectric layer
    Patent number: 7253063
    Abstract: A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiOx?2, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: August 7, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: David A Muller, Gregory L. Timp, Glen David Wilk
  • Silicon oxide based gate dielectric layer
    Patent number: 6844076
    Abstract: A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide SiOX?2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: January 18, 2005
    Assignee: Lucent Technologies Inc.
    Inventors: David A Muller, Gregory L. Timp
  • SILICON OXIDE BASED GATE DIELECTRIC LAYER
    Publication number: 20040097026
    Abstract: A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiOX≦2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 20, 2004
    Inventors: David A. Muller, Gregory L. Timp
  • Silicon oxide based gate dielectric layer
    Patent number: 6693051
    Abstract: A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiOX≦2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: February 17, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: David A Muller, Gregory L. Timp
  • Composite gate dielectric layer
    Publication number: 20030017715
    Abstract: A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiOx≦2, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.
    Type: Application
    Filed: August 23, 2002
    Publication date: January 23, 2003
    Inventors: David A. Muller, Gregory L. Timp, Glen David Wilk
  • Composite gate dielectric layer
    Publication number: 20020102797
    Abstract: A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiOX≦2, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Inventors: David A. Muller, Gregory L. Timp, Glen David Wilk
  • Silicon oxide based gate dielectric layer
    Publication number: 20020100946
    Abstract: A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiOX≦2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Inventors: David A. Muller, Gregory L. Timp
  • Scanning depletion microscopy for carrier profiling
    Patent number: 6417673
    Abstract: In an imaging system for carrier profiling of a device structure, a doped semiconductor tip is utilized as an active dynamic sensing element for successively probing spaced-apart portions of the structure. At each probe position, the bias voltage applied between the tip and the structure is varied. While the bias voltage is being varied, a measurement is taken of the change in capacitance that occurs between the tip and the structure. These measurements provide an accurate high-resolution high-contrast image that is representative of the carrier profile of the probed portions of the device structure.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: July 9, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Rafael Nathan Kleiman, Megan Lorraine O'Malley, Gregory L. Timp
  • Electron tuned quantum well device
    Patent number: 4942437
    Abstract: A quantum well type signal translating device is constructed by providing an appendage in which a reflected wave can be employed to introduce constructive or destructive interference in electron wave conduction at the heterojunction.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: July 17, 1990
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Fowler, Gregory L. Timp