Patents by Inventor Gregory L. Tucker

Gregory L. Tucker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory control architecture for high-speed transfer operations
    Patent number: 5737761
    Abstract: A subsystem architecture for direct memory access of random access memory (RAM) which performs block transfers of adjacent units of memory from one memory location to another. The architecture comprises a RAM array with write enable capability, serial access memory (SAM) registers, an alignment unit, and controller. An embodiment is described which performs bit-block transfers (BitBLTs) of pixel data within a graphical user interface (GUI) subsystem which utilizes Triple-ported Dynamic RAM (TPDRAM). The BitBLT is broken up into four cycles which handle the transfer of all possible combinations of units of adjacent memory utilizing the entire bandwidth of the port writing to RAM. The architecture allows operations to be pipelined.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: April 7, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Stephen Holland, Gregory L. Tucker
  • Memory control architecture for high speed transfer options
    Patent number: 5623624
    Abstract: A subsystem architecture for direct memory access of random access memory (RAM) which performs block transfers of adjacent units of memory from one memory location to another. The architecture comprises a RAM array with write enable capability, serial access memory (SAM) registers, an alignment unit, and controller. An embodiment is described which performs bit-block transfers (BitBLTs) of pixel data within a graphical user interface (GUI) subsystem which utilizes Triple-ported Dynamic RAM (TPDRAM). The BitBLT is broken up into four cycles which handle the transfer of all possible combinations of units of adjacent memory utilizing the entire bandwidth of the port writing to RAM. The architecture allows operations to be pipelined.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: April 22, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Stephen Holland, Gregory L. Tucker