Abstract: A transmitting device may implement a checksum for integrity verification for a message page during an auto-negotiation period. The checksum may provide redundancy to ensure the integrity of the message page after transmission. The checksum may be calculated based on the message page and appended to the message page for transmission. A receiving device may receive the message page with the appended checksum and calculate a checksum locally using the received message page. The calculated and received checksum may be compared by the receiving device to verify the integrity of the message.

Abstract: A network device includes a communication interface and a transmitter coupled to the communication interface. The transmitter is configured to determine to start an auto-negotiation page with a link partner, and transmit, through the communication interface, a start delimiter for the auto-negotiation page. The transmitter transmits the start delimiter by transmitting a first pulse comprising a first encoding violation, followed by a second pulse comprising a second encoding violation. The transmitter may shorten the first pulse and the second pulse relative to a different pre-defined start delimiter to define spectral content for the first pulse and the second pulse that passes different first and second receiver filters in the link partner for different first and second communication standards.

Abstract: A transmitting device may implement a checksum for integrity verification for a message page during an auto-negotiation period. The checksum may provide redundancy to ensure the integrity of the message page after transmission. The checksum may be calculated based on the message page and appended to the message page for transmission. A receiving device may receive the message page with the appended checksum and calculate a checksum locally using the received message page. The calculated and received checksum may be compared by the receiving device to verify the integrity of the message.

Abstract: A network device includes a communication interface and a transmitter coupled to the communication interface. The transmitter is configured to determine to start an auto-negotiation page with a link partner, and transmit, through the communication interface, a start delimiter for the auto-negotiation page. The transmitter transmits the start delimiter by transmitting a first pulse comprising a first encoding violation, followed by a second pulse comprising a second encoding violation. The transmitter may shorten the first pulse and the second pulse relative to a different pre-defined start delimiter to define spectral content for the first pulse and the second pulse that passes different first and second receiver filters in the link partner for different first and second communication standards.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A sequence generator is configured to be re-initialized to a value selected derived from a candidate group that is derived from a predetermined value. If and when the re-initializing is performed, it is fully performed within about one clock cycle of setting the sequence generator to the predetermined value. The sequence generator is optionally initialized by a local processor to which it is operatively coupled, after which the processor receives one sequence value each cycle.

Abstract: A method of encoding data includes representing the data as number(s) in a first base. The method further includes converting the number(s) into a number(s) in a second base. The resultant number in the second base can be viewed as data suitable for encoding using an ECC algorithm. After being ECC encoded, the data may be further modulation encoded. Modulation encoding may include transforming each symbol to a value that constrains run lengths of a binary value (e.g., zero). A decoding method and system checks a received data block for erroneous symbols, maps each received, encoded symbol to an associated ECC-encoded transform pair. The ECC encoded data may be decoded and corrected using the ECC and the locations of identified erroneous symbols. Finally, the corrected data sequence is converted from the second base back to the first base, from which the original data is retrieved.