Patents by Inventor Gregory Louis Ranson

Gregory Louis Ranson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7370308
    Abstract: A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: May 6, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Charles Corey Pie, Gregory Louis Ranson
  • Patent number: 6996792
    Abstract: A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: February 7, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Charles Corey Pie, Gregory Louis Ranson
  • Publication number: 20030145298
    Abstract: A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
    Type: Application
    Filed: January 29, 2002
    Publication date: July 31, 2003
    Inventors: Charles Corey Pie, Gregory Louis Ranson