Abstract: A medical device for treating a heart having a faulty heart valve is disclosed. The medical device comprises a ligature including a first anchoring member and a second anchoring member is used. The ligature is percutaneously deployable into a patient with a faulty heart valve wherein the first anchoring member to anchor to a first tissue area of the heart and the second anchoring member to anchor to a second tissue area of the heart.

Abstract: A medical device for treating a heart having a faulty heart valve is disclosed. The medical device comprises a ligature including a first anchoring member and a second anchoring member is used. The ligature is percutaneously deployable into a patient with a faulty heart valve wherein the first anchoring member to anchor to a first tissue area of the heart and the second anchoring member to anchor to a second tissue area of the heart.

Abstract: A medical device for treating a heart having a faulty heart valve is disclosed. The medical device comprises a ligature including a first anchoring member and a second anchoring member is used. The ligature is percutaneously deployable into a patient with a faulty heart valve wherein the first anchoring member to anchor to a first tissue area of the heart and the second anchoring member to anchor to a second tissue area of the heart.

Abstract: Disclosed are printed articles that may be used to decorate substrates.

Abstract: A medical device for treating a defective heart valve. The medical device comprises a distal anchoring member for disposing in a blood vessel. A proximal anchoring member for disposing in or at an entrance of the blood vessel. A telescoping assembly coupling at a first end to the distal anchoring member and at a second end to the proximal anchoring member. The telescoping assembly is deployable into the blood vessel. The telescoping assembly reduces a distance between the distal anchoring member and the proximal anchoring member, wherein the telescoping assembly comprises of at least two members capable of sliding into each other giving the telescoping assembly adjustable lengths.

Abstract: A technique for random early drop (RED) with per-hop-behavior (PHB) biasing involves breaking RED parameters into queue-specific parameters and packet-specific parameters. Each queue has associated queue-specific parameters. Each packet has an associated traffic class. The packet-specific parameters are related to the traffic class of the packet. The queue-specific and packet-specific parameters are then both used in RED procedures, thereby providing a PHB bias from using packet-specific parameters. The technique provides for absolute queue size support that can be dynamically changed based upon available memory resource levels.

Abstract: A medical device for treating a heart having a faulty heart valve is disclosed. The medical device comprises a ligature including a first anchoring member and a second anchoring member is used. The ligature is percutaneously deployable into a patient with a faulty heart valve wherein the first anchoring member to anchor to a first tissue area of the heart and the second anchoring member to anchor to a second tissue area of the heart.

Abstract: A cache controller is intimately associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where it is sent to the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Abstract: A technique for random early drop (RED) with per-hop-behavior (PHB) biasing involves breaking RED parameters into queue-specific parameters and packet-specific parameters. Each queue has associated queue-specific parameters. Each packet has an associated traffic class. The packet-specific parameters are related to the traffic class of the packet. The queue-specific and packet-specific parameters are then both used in RED procedures, thereby providing a PHB bias from using packet-specific parameters. The technique provides for absolute queue size support that can be dynamically changed based upon available memory resource levels.

Abstract: A cache controller is intimately associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where it is sent to the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the IRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Abstract: A decentralized exception processing system includes a plurality of local exception units. Each local exception unit is coupled to process local exception signals from one or more processing resources that are proximate to it. Each local exception unit generates local commit signals, using order information for the instruction in an issue group and any local exception signals it receives. The local commit signals are combined to generate a global commit signal for each instruction in the issue group. Local exception signals are collected at a selected one of the local exception units and processed to generate a global exception unit. The selected local exception unit resteers control of the processing resources to an exception handler associated with the global exception unit.

Abstract: A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with entries in the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Abstract: A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.

Abstract: A cache controller for a set associative cache selectively remaps predetermined bits of the cache address so as to confine data from a single memory page to a particular block of the cache memory. When changing a memory page, only the particular block of the cache in which data from that page may be stored is flushed, thereby preserving the remaining contents of the cache.

Abstract: A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.

Abstract: A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.