Patents by Inventor Gregory MUTHLER
Gregory MUTHLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250104333Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
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Publication number: 20250104332Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Inventors: Samuli LAINE, Timo AILA, Tero KARRAS, Gregory MUTHLER, William P. NEWHALL, JR., Ronald C BABICH, JR., Craig KOLB, Ignacio LLAMAS, John BURGESS
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Patent number: 12260486Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.Type: GrantFiled: September 16, 2022Date of Patent: March 25, 2025Assignee: NVIDIA CorporationInventors: John Burgess, Gregory Muthler, Nikhil Dixit, Henry Moreton, Yury Uralsky, Magnus Andersson, Marco Salvi, Christoph Kubisch
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Publication number: 20250095276Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.Type: ApplicationFiled: November 27, 2024Publication date: March 20, 2025Inventors: Gregory MUTHLER, John BURGESS
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Publication number: 20250095277Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.Type: ApplicationFiled: November 29, 2024Publication date: March 20, 2025Inventors: Gregory MUTHLER, John BURGESS, Ronald Charles BABICH, William Parsons Newhall
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Patent number: 12249022Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.Type: GrantFiled: September 16, 2022Date of Patent: March 11, 2025Assignee: NVIDIA CorporationInventors: John Burgess, Gregory Muthler, Nikhil Dixit, Henry Moreton, Yury Uralsky, Magnus Andersson, Marco Salvi, Christoph Kubisch
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Publication number: 20250046004Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.Type: ApplicationFiled: October 22, 2024Publication date: February 6, 2025Inventors: Gregory MUTHLER, John BURGESS
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Publication number: 20250046003Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.Type: ApplicationFiled: October 21, 2024Publication date: February 6, 2025Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Timo VIITANEN, Levi OLIVER
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Patent number: 12198252Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.Type: GrantFiled: September 16, 2022Date of Patent: January 14, 2025Assignee: NVIDIA CORPORATIONInventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
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Patent number: 12198256Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.Type: GrantFiled: November 14, 2023Date of Patent: January 14, 2025Assignee: NVIDIA CorporationInventors: Gregory Muthler, John Burgess, Ronald Charles Babich, Jr., William Parsons Newhall, Jr.
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Patent number: 12198251Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.Type: GrantFiled: September 16, 2022Date of Patent: January 14, 2025Assignee: NVIDIA CORPORATIONInventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
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Patent number: 12198255Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.Type: GrantFiled: September 21, 2023Date of Patent: January 14, 2025Assignee: NVIDIA CORPORATIONInventors: Samuli Laine, Timo Aila, Tero Karras, Gregory Muthler, William P. Newhall, Jr., Ronald C Babich, Jr., Craig Kolb, Ignacio Llamas, John Burgess
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Patent number: 12190435Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.Type: GrantFiled: October 10, 2023Date of Patent: January 7, 2025Assignee: NVIDIA CORPORATIONInventors: Gregory Muthler, John Burgess
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Publication number: 20250004947Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.Type: ApplicationFiled: September 11, 2024Publication date: January 2, 2025Inventors: Gregory A. MUTHLER, Timo AILA, Tero KARRAS, Samuli LAINE, William Parsons NEWHALL, JR., Ronald Charles BABICH, JR., John BURGESS, Ignacio LLAMAS
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Patent number: 12159342Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.Type: GrantFiled: May 20, 2022Date of Patent: December 3, 2024Assignee: NVIDIA CorporationInventors: Gregory Muthler, John Burgess
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Patent number: 12154214Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.Type: GrantFiled: September 9, 2022Date of Patent: November 26, 2024Assignee: NVIDIA CorporationInventors: Gregory Muthler, John Burgess, Magnus Andersson, Timo Viitanen, Levi Oliver
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Publication number: 20240362851Abstract: A bounding volume is used to approximate the space an object occupies. If a more precise understanding beyond an approximation is required, the object itself is then inspected to determine what space it occupies. Often, a simple volume (such as an axis-aligned box) is used as bounding volume to approximate the space occupied by an object. But objects can be arbitrary, complicated shapes. So a simple volume often does not fit the object very well. That causes a lot of space that is not occupied by the object to be included in the approximation of the space being occupied by the object. Hardware-based techniques are disclosed herein, for example, for efficiently using multiple bounding volumes (such as axis-aligned bounding boxes) to represent, in effect, an arbitrarily shaped bounding volume to better fit the object, and for using such arbitrary bounding volumes to improve performance in applications such as ray tracing.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Inventors: Gregory MUTHLER, John BURGESS
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Patent number: 12124378Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.Type: GrantFiled: April 20, 2023Date of Patent: October 22, 2024Assignee: NVIDIA CorporationInventors: Gregory A. Muthler, Timo Aila, Tero Karras, Samuli Laine, William Parsons Newhall, Jr., Ronald Charles Babich, Jr., John Burgess, Ignacio Llamas
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Patent number: 12106423Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.Type: GrantFiled: September 16, 2022Date of Patent: October 1, 2024Assignee: NVIDIA CORPORATIONInventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
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Publication number: 20240303906Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.Type: ApplicationFiled: May 20, 2024Publication date: September 12, 2024Inventors: Gregory MUTHLER, John BURGESS, James ROBERTSON, Magnus ANDERSON