Patents by Inventor Gregory N. Carter

Gregory N. Carter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5943591
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 24, 1999
    Assignee: VLSI Technology
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5795815
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: August 18, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5686171
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: November 11, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers