Patents by Inventor Gregory Onufer
Gregory Onufer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12277041Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: GrantFiled: June 9, 2023Date of Patent: April 15, 2025Assignee: Oracle International CorporationInventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Publication number: 20230418715Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: ApplicationFiled: June 9, 2023Publication date: December 28, 2023Inventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Patent number: 11709742Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: GrantFiled: February 2, 2022Date of Patent: July 25, 2023Assignee: Oracle International CorporationInventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Publication number: 20220156075Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: ApplicationFiled: February 2, 2022Publication date: May 19, 2022Inventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Patent number: 11263012Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: GrantFiled: January 6, 2020Date of Patent: March 1, 2022Assignee: Oracle International CorporationInventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Patent number: 10983921Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.Type: GrantFiled: February 3, 2020Date of Patent: April 20, 2021Assignee: Oracle International CorporationInventors: John Feehrer, Patrick Stabile, Gregory Onufer, John Johnson
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Publication number: 20200210185Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: ApplicationFiled: January 6, 2020Publication date: July 2, 2020Inventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Publication number: 20200174946Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.Type: ApplicationFiled: February 3, 2020Publication date: June 4, 2020Inventors: John Feehrer, Patrick Stabile, Gregory Onufer, John Johnson
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Patent number: 10552340Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.Type: GrantFiled: February 28, 2017Date of Patent: February 4, 2020Assignee: Oracle International CorporationInventors: John Feehrer, Patrick Stabile, Gregory Onufer, John Johnson
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Patent number: 10528351Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: GrantFiled: June 26, 2017Date of Patent: January 7, 2020Assignee: Oracle International CorporationInventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Publication number: 20180246817Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: John Feehrer, Patrick Stabile, Gregory Onufer, John Johnson
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Publication number: 20170293539Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Patent number: 9710273Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: GrantFiled: November 21, 2014Date of Patent: July 18, 2017Assignee: Oracle International CorporationInventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Publication number: 20160147534Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.Type: ApplicationFiled: November 21, 2014Publication date: May 26, 2016Inventors: James Lewis, Paul Jordan, Gregory Onufer, Ali Vahidsafa
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Publication number: 20070162625Abstract: A method and apparatus for delivering a device driver to an operating system without user intervention. One or more operating systems (e.g., different operating system programs, different versions of one operating system) execute on a computer platform. During booting of an operating system a device is identified for which a driver is needed. The driver is requested from a service processor of the platform, which includes memory or storage for storing multiple device drivers (or multiple versions of one driver, for different operating systems). The driver is retrieved from the service processor's storage and delivered to the operating system.Type: ApplicationFiled: January 11, 2006Publication date: July 12, 2007Inventors: Ashley Saulsbury, David Redman, Gregory Onufer, John Johnson
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Publication number: 20050022078Abstract: A system maintains a copy of data stored in a first memory device in a redundant distinct second memory device. Upon detecting an uncorrectable error in the first memory device, the system then relies on the copy of the data in the second memory device. The system, once it starts relying on the data in the second memory device, may then test the first memory device to determine if the uncorrectable error was due to a physical problem or a transient event. If the first memory device is then found to be working correctly, it may, in turn, become a redundant memory device for the second memory device.Type: ApplicationFiled: July 21, 2003Publication date: January 27, 2005Inventors: Srinivasan Subramanian, John Johnson, Gregory Onufer