Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

Abstract: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.

Abstract: A memory device has at least one sub array of memory cells having data columns and at least one spare sub array having spare columns. In one embodiment the sub array of memory cells and the sub array having spare columns are the same sub array. Individual elements in the sub arrays of memory cells can be repaired using an individual element from the spare sub array.

Abstract: A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.

Abstract: A memory cell array employs “source-biasing”, wherein a bias voltage is applied to the sources of one or more FETs within a memory cell to reduce their “off” state sub-threshold leakage currents. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs, and ground for FETs which are being read. A plurality of source-bias circuits provides the selectively switched bias voltages to the memory cells in the array.