Patents by Inventor Gregory Pickrell

Gregory Pickrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218497
    Abstract: A disclosed switching apparatus, such as a circuit breaker, includes a transistor switch circuit connected between a power input terminal and a load terminal, and, connected to the power input terminal and bypassing the transistor switch circuit, a switchable bypass leg that is optically switched by a series-connected photoconductive semiconductor switch (PCSS). The transistor switch circuit includes at least one cascade of three or more series-connected transistors, and at least one resistor network configured to divide a voltage from a voltage source across a cascade of series-connected transistors. Operating the switch apparatus includes detecting whether a sensed electric current is in a fault condition, opening the transistor switch circuit upon detecting a fault condition, and then closing the PCSS so that the electric current is diverted onto a switchable bypass path. The opening of the transistor switch circuit comprises turning OFF a normally-ON transistor switch circuit.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 4, 2025
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, UNM Rainforest Innovations
    Inventors: Gregory Pickrell, Jason Christopher Neely, Lee Gill, Jacob Mueller, Luciano Andres Garcia Rodriguez, Jack David Flicker, Emily Ann Schrock, Robert Kaplar, Harold P. Hjalmarson, Jane Lehr
  • Patent number: 7767480
    Abstract: A method of manufacturing a distributed Bragg reflector (DBR) in group III-V semiconductor compounds with improved optical and electrical characteristics is provided. A selected DBR structure is achieved by sequential exposure of a substrate to predetermined combinations of the elemental sources to produce a pair of DBR layers of compound alloys and a graded region including one or more discrete additional layers between the DBR layers of intermediate alloy composition. Exposure durations and combinations of the elemental sources in each exposure are predetermined by DBR design characteristics.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: August 3, 2010
    Assignee: Opticomp Corporation
    Inventors: Gregory Pickrell, Duane A. Louderback, Peter Guilfoyle
  • Patent number: 7535944
    Abstract: An optical coupler comprises first and second mirrors. The first mirror is positioned with respect to the second mirror so that a resonant cavity is defined between them. A waveguide structure is positioned in the resonant cavity and includes a photonic crystal coupler. A thickness of the resonant cavity is selected so that a phase matching condition is satisfied for resonance in the resonant cavity. At least one of the first and second mirrors may be formed from a structure in an optoelectronic device. Alternatively, at least one of the first and second mirrors is formed from a semiconductor layer. At least one of the first and second mirrors may be formed as a semiconductor distributed bragg reflector, or as a dielectric distributed bragg reflector. At least one of the first and second mirrors may be a mirror in a vertical cavity surface emitting laser (VCSEL) structure.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: May 19, 2009
    Assignee: Opticomp Corporation
    Inventors: Peter Guilfoyle, Jongwoo Kim, Duane A. Loudeback, Gregory Pickrell
  • Publication number: 20080296619
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 4, 2008
    Applicant: Board of Trustees of the University of Illinois
    Inventors: Kuang Chien Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John H. Epple, Gregory Pickrell
  • Patent number: 7407863
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 5, 2008
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Kuang Chien Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John H. Epple, Gregory Pickrell
  • Publication number: 20050074927
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Inventors: Kuang Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John Epple, Gregory Pickrell