Abstract: According to some embodiments, an input symbol may be received, and a hard symbol may be generated from the input symbol. A probability associated with the hard symbol may be calculated along with a probability associated with a previous hard symbol. An enhanced symbol may then be determined as a function of a comparison between the probability associated the hard symbol and the previous hard symbol.

Abstract: A noise level of an input signal is determined by a noise calculation module. based on the noise level, a boundary setting module sets a reduced constellation boundary interval. This reduced constellation boundary interval is employed by an equalizer to perform adaptive equalization of the input signal.

Abstract: According to some embodiments, an input symbol may be received, and a hard symbol may be generated from the input symbol. A probability associated with the hard symbol may be calculated along with a probability associated with a previous hard symbol. An enhanced symbol may then be determined as a function of a comparison between the probability associated the hard symbol and the previous hard symbol.

Abstract: According to some embodiments, an input symbol may be received, and a hard symbol may be generated from the input symbol. A probability associated with the hard symbol may be calculated along with a probability associated with a previous hard symbol. An enhanced symbol may then be determined as a function of a comparison between the probability associated the hard symbol and the previous hard symbol.

Abstract: According to some embodiments, an input symbol may be received, and a hard symbol may be generated from the input symbol. A probability associated with the hard symbol may be calculated along with a probability associated with a previous hard symbol. An enhanced symbol may then be determined as a function of a comparison between the probability associated the hard symbol and the previous hard symbol.

Abstract: An architecture and method for flexible preamble processing is disclosed herein. The preamble processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.

Abstract: An architecture and method for flexible preamble processing is disclosed herein. The preamble processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.

Abstract: A method for designing an integrated circuit comprises the step of selecting a system-level parameterized module that performs a specified type of function. The method also includes the steps of specifying values for parameters of the selected system-level module and generating a netlist file from the selected system-level module. In one embodiment, the system-level parameterized module is selected from a family of system-level parameterized modules that each perform a particular function within different parameter ranges.