Abstract: Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface.

Abstract: Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate the wireless transmission and reception of data and/or commands from and to host component that requests access to the memory and the data stored therein. The memory module can dynamically switch between one wireless communication technology to another based on signal strength, signal quality, the distance between the memory module and a host component, power usage, as well as other criteria to facilitate an optimal data transmission or throughput rate.

Abstract: Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate the wireless transmission and reception of data and/or commands from and to host component that requests access to the memory and the data stored therein. The memory module can dynamically switch between one wireless communication technology to another based on signal strength, signal quality, the distance between the memory module and a host component, power usage, as well as other criteria to facilitate an optimal data transmission or throughput rate.

Abstract: Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface.

Abstract: Systems and methods that can facilitate providing a flexible flash interface component that can accommodate communicating with almost any flash memory component (e.g., Open NAND Flash Interface (ONFI) compliant and ONFI noncompliant flash memory). A micro-operations component can contain one or more micro-operation that can be used to execute commands within the flash interface component. To facilitate a flexible flash interface, the micro-operations can include such commands as, but are not limited to, sending a command to the flash memory, sending a row address, sending a column address, transmit data (TXD), receive data (RXD), have the flash interface wait for a ready signal from the flash memory, read a status register from a flash memory, and/or provide an end of sequence (EOS) indication to the flash interface, for example.

Abstract: An integrated circuit (20) includes an ESD protection circuit (50) to protect it from excessive electrostatic discharge voltages. The ESD protection circuit (50) includes a diode (51) in series with a silicon controlled rectifier (SCR) (60) connected between an input signal line (42) and a power supply voltage terminal. Unlike conventional protection circuits, the ESD protection circuit (50) allows the voltage on the input signal line (42) to extend well beyond positive and negative power supply potentials, and only becomes conductive to discharge voltages which are outside of this extended range.

Abstract: A pseudo-static mask option register (50) combines features of both a continuous refresh design and a static latched mask option register design. Pseudo-static mask option register (50) removes a mask option function from a main user memory (48) such that the functionality of the mask option register (50) is not limited by a plurality of electrical characteristics of the main use memory (48). When using the pseudo-static mask option register (50), a memory state of each memory bit (64, 66, 68) is read at any time. Additionally, a portion of the memory bits (64, 66, 68) is periodically refreshed such that pseudo-static mask option register (50) maintains an integrity of a value stored therein while minimizing power consumption. Pseudo-static mask option register (50) also has a non-volatile output state to allow emulation of mask options which are vulnerable to electrical disturbances.

Abstract: A method and apparatus for preventing a data processing system (10) from entering a non-recoverable state. In one form, the present invention uses a pin (40) to indicate whether or not the execution of a non-recoverable instruction is legal. If the pin indicates that the execution of the instruction is legal, then the instruction is executed and the data processing system (10) is placed into a state that requires an external stimulus in order to recover. If the pin indicates that the execution of the instruction is illegal, then the instruction is not permitted to place the data processing system (10) into a state that requires an external stimulus in order to recover. Instead, an internal recovery mechanism is provided which returns the data processing system (10) to normal processing.

Abstract: A nonvolatile memory (28) in a data processor (10) is capable of being progressively programmed and/or accessed in a user determined number of sections. A user can program and/or access what appears to the user to be reprogrammable nonvolatile memory (28) at a same address when in actuality the user is programming and accessing sequential sections of nonvolatile memory (28). Nonvolatile information stored in nonvolatile control bits (20) is used to control which section of the nonvolatile memory is connected to a communication bus and is thus accessible to the user. When the user desires to write and/or access a new section of nonvolatile memory (28), either the user directly asserts one of the nonvolatile control bits (20) using software, or the nonvolatile control (24) asserts one of the nonvolatile control bits (20) using hardware.

Abstract: A method and apparatus for performing power on reset initialization in a data processing system (40). In one form, the present invention uses a circuit (71) to ensure that a node (65) always power up to the correct logic level. This node (65) can then be used to initialize a latch (83) so that the latch (83) always drives a predetermined logic level at its data output when the latch (83) powers up. The data output of latch (83) is a Power On Reset signal which is asserted during power on reset initialization and which is negated when power on reset initialization is completed.

Abstract: A microcontroller is provided having an on-chip electrically erasable programmable read-only-memory (EEPROM), which is user programmable via a programming register. The microcontroller includes a low voltage program inhibit (LVPI) circuit which is combined with the existing EEPROM design. By integrating the LVPI circuit into the EEPROM, the EEPROM may be protected without disabling the entire data processing system. If the supply voltage (V.sub.DD) falls below a predetermined voltage level, the LVPI circuit inhibits the use of the EEPROM programming register, thereby preventing the CPU from programming or erasing the EEPROM. A comparator in the LVPI circuit compares a precision reference voltage to a voltage divided off of the power supply (V.sub.DD), and provides a output signal to the EEPROM programming register. During normal operation, the comparator output signal is a logic low, which enables the user to program or erase the EEPROM, via the programming register.