Abstract: A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.

Abstract: Systems, methodologies, media and other embodiments associated with peak detectors are described. One exemplary system embodiment includes a voltage peak detector comprising a first detector logic configured to detect a peak voltage of an input signal. The first detector logic has a circuit behavior that produces a leakage current that may alter the peak voltage. The system can also include a second detector logic configured to replicate the circuit behavior of the first detector logic including being configured to produce a replica leakage current that is equivalent to the leakage current. The second detector logic can be operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.