Patents by Inventor Gregory RAYMOND
Gregory RAYMOND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240126560Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Inventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A.T. Jones, Jayant Thakur
-
Patent number: 11960416Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.Type: GrantFiled: December 21, 2021Date of Patent: April 16, 2024Assignee: Texas Instruments IncorporatedInventors: Daniel Brad Wu, Abhishek Shankar, Mihir Narendra Mody, Gregory Raymond Shurtz, Jason A. T. Jones, Hemant Vijay Kumar Hariyani
-
Publication number: 20240093186Abstract: The disclosure provides, e.g., compositions, systems, and methods for targeting, editing, modifying, or manipulating a host cell's genome at one or more locations in a DNA sequence in a cell, tissue, or subject. Gene modifying systems for treating cystic fibrosis, e.g., in subjects having a mutation resulting in F508del, are described.Type: ApplicationFiled: September 20, 2023Publication date: March 21, 2024Inventors: Robert Charles Altshuler, Anne Helen Bothmer, Daniel Raymond Chee, Cecilia Giovanna Silvia Cotta-Ramusino, Kyusik Kim, Randi Michelle Kotlar, Gregory David McAllister, Aamir Mir, Ananya Ray, Nathaniel Roquet, Carlos Sanchez, Barrett Ethan Steinberg, Robert James Citorik, William Edward Salomon, William Querbes, Luciano Henrique Apponi, Zhan Wang
-
Publication number: 20240084334Abstract: The disclosure provides, e.g., compositions, systems, and methods for targeting, editing, modifying, or manipulating a host cell's genome at one or more locations in a DNA sequence in a cell, tissue, or subject. Gene modifying systems for treating alpha-1 antitrypsin deficiency (AATD) are described.Type: ApplicationFiled: September 18, 2023Publication date: March 14, 2024Inventors: Robert Charles Altshuler, Anne Helen Bothmer, Daniel Raymond Chee, Cecilia Giovanna Silvia Cotta-Ramusino, Kyusik Kim, Randi Michelle Kotlar, Gregory David McAllister, Ananya Ray, Nathaniel Roquet, Carlos Sanchez, Barrett Ethan Steinberg, William Edward Salomon, Robert James Citorik, William Querbes, Luciano Henrique Apponi, Zhan Wang
-
Publication number: 20240082429Abstract: The disclosure provides, e.g., compositions, systems, and methods for targeting, editing, modifying, or manipulating a host cell's genome at one or more locations in a DNA sequence in a cell, tissue, or subject. Gene modifying systems for treating phenylketonuria (PKU) are described.Type: ApplicationFiled: October 26, 2023Publication date: March 14, 2024Inventors: Robert Charles Altshuler, Anne Helen Bothmer, Daniel Raymond Chee, Cecilia Giovanna Silvia Cotta-Ramusino, Kyusik Kim, Randi Michelle Kotlar, Gregory David McAllister, Ananya Ray, Nathaniel Roquet, Carlos Sanchez, Barrett Ethan Steinberg, William Edward Salomon, Robert James Citorik, William Querbes, Luciano Henrique Apponi, Zhan Wang
-
Patent number: 11914761Abstract: Systems and methods are provided to create training data, validate, deploy and test artificial intelligence (AI) systems in a virtual development environment, incorporating virtual spaces, objects, machinery, devices, subsystems, and actual human action and behavior.Type: GrantFiled: May 5, 2023Date of Patent: February 27, 2024Assignee: SAEC/Kinetic Vision, Inc.Inventors: Richard Raymond Schweet, Bendenetto Christopher Ruggiero, Kyle Robert Hartshorn, Gregory Ryan Sweeney, Kyle Dean Cypher, Melissa Yenni Scharf, Emily Ann Meyer, Alec Brenders Lisy, Jeremy David Jarrett, Matthew David Fye
-
Patent number: 11880333Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).Type: GrantFiled: May 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Jason A. T. Jones, Sriramakrishnan Govindarajan, Mihir Narendra Mody, Kishon Vijay Abraham Israel Vijayponraj, Bradley Douglas Cobb, Sanand Prasad, Gregory Raymond Shurtz, Martin Jeffrey Ambrose, Jayant Thakur
-
Patent number: 11853772Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: GrantFiled: August 16, 2022Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A. T. Jones, Jayant Thakur
-
Publication number: 20230350811Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Sriramakrishnan GOVINDARAJAN, Gregory Raymond SHURTZ, Mihir Narendra MODY, Charles Lance FUOCO, Donald E. STEISS, Jonathan Elliot BERGSAGEL, Jason A.T. JONES
-
Publication number: 20230326002Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.Type: ApplicationFiled: June 12, 2023Publication date: October 12, 2023Inventors: Mihir Narendra MODY, JR., Veeramanikandan RAJU, Niraj NANDAN, Samuel Paul VISALLI, Jason A.T. JONES, Kedar Satish CHITNIS, Gregory Raymond SHURTZ, Prithvi Shankar YEYYADI ANANTHA, Sriramakrishnan GOVINDARAJAN
-
Publication number: 20230244557Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Inventors: Kedar Satish Chitnis, Charles Lance Fuoco, Sriramakrishnan Govindarajan, Mihir Narendra Mody, William A. Mills, Gregory Raymond Shurtz, Amritpal Singh Mundra
-
Patent number: 11715188Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.Type: GrantFiled: February 28, 2022Date of Patent: August 1, 2023Assignee: Texas Instruments IncorporatedInventors: Mihir Narendra Mody, Veeramanikandan Raju, Niraj Nandan, Samuel Paul Visalli, Jason A. T. Jones, Kedar Satish Chitnis, Gregory Raymond Shurtz, Prithvi Shankar Yeyyadi Anantha, Sriramakrishnan Govindarajan
-
Patent number: 11693787Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: GrantFiled: February 9, 2021Date of Patent: July 4, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Lance Fuoco, Donald E. Steiss, Jonathan Elliot Bergsagel, Jason A.T. Jones
-
Publication number: 20230195658Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Daniel Brad WU, Abhishek SHANKAR, Mihir Narendra MODY, Gregory Raymond SHURTZ, Jason A. T. JONES, Hemant Vijay Kumar HARIYANI
-
Publication number: 20230185904Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventors: Kedar Satish CHITNIS, Mihir Narendra MODY, Amritpal Singh MUNDRA, Yashwant DUTT, Gregory Raymond SHURTZ, Robert John TIVY
-
Patent number: 11656925Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.Type: GrantFiled: December 30, 2020Date of Patent: May 23, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kedar Satish Chitnis, Charles Lance Fuoco, Sriramakrishnan Govindarajan, Mihir Narendra Mody, William A. Mills, Gregory Raymond Shurtz, Amritpal Singh Mundra
-
Publication number: 20230016766Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Inventors: Rajat SAGAR, Mihir Narendra MODY, Anthony Joseph LELL, Gregory Raymond SHURTZ
-
Publication number: 20230004855Abstract: Techniques for executing machine learning (ML) models including receiving an indication to execute an ML model on a processing core; determining a resource allocation for executing the ML model on the processing core; determining that a layer of the ML model will use a first amount of the resource, wherein the first amount is more than an amount of the resource allocated; determining that an adaptation may be applied to executing the layer of the ML model; executing the layer of the ML model using the adaptation, wherein executing the layer using the adaptation reduces the first amount of the resource used by the layer as compared to executing the layer without using the adaptation; and outputting a result of the ML model based on the executed layer.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Mihir Narendra MODY, Kumar DESAPPAN, Gregory Raymond SHURTZ, Jason A.T. JONES
-
Patent number: 11530213Abstract: The present invention provides a compound of formula (I) or a pharmaceutically acceptable salt thereof; Wherein R1, R3-R6, X2 and X3 are as defined herein, a method for manufacturing the compounds of the invention, and its therapeutic uses. The present invention further provides a combination of pharmacologically active agents and a pharmaceutical composition.Type: GrantFiled: October 15, 2020Date of Patent: December 20, 2022Assignee: Novartis AGInventors: Guillaume Barbe, Gregory Raymond Bebernitz, Sicong Geng, Hatice Belgin Gulgeze Efthymiou, Lv Liao, Fupeng Ma, Ruowei Mo, David Thomas Parker, Yunshan Peng, Stefan Peukert, Nichola Smith, Ken Yamada, Kayo Yasoshima
-
Publication number: 20220391219Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: August 16, 2022Publication date: December 8, 2022Inventors: Sriramakrishnan GOVINDARAJAN, Denis Roland BEAUDOIN, Gregory Raymond SHURTZ, Santhanakrishnan Badri NARAYANAN, Mark Adrian BRYANS, Mihir Narendra MODY, Jason A.T. JONES, Jayant THAKUR