Abstract: A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.

Abstract: In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.

Abstract: A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.

Abstract: Systems and methods are disclosed for implementing configuration memory on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers are implemented between sections of a column of memory. The buffers may provide buffering for data lines extending through the column of memory.

Abstract: Systems and methods are disclosed for implementing configuration memory on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers are implemented between sections of a column of memory. The buffers may provide buffering for data lines extending through the column of memory.