Abstract: The invention is a receiver and a method of receiving data having a preferred application in a satellite receiver in accordance with the invention includes a memory (114) including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal from a plurality channels (X, Y and Z) and outputs the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and a decoder (116), responsive to the data groups, which decodes the data samples within the data groups and outputs decoded data samples.

Abstract: A satellite based cellular communications system (10) for servicing multiple user terminals (14) is provided. The satellite based cellular communications system (10) includes at least one processing communications satellite (12) which supports communications uplinks (16) and communications downlinks (18) between multiple user terminals (14). A network operations center (24) having a central control processor (26) communicates with the processing communication satellite (12) on the communications uplinks (16) and the communications downlinks (18). The central control processor (26) minimizes intra-system interference between the multiple user terminals (14) by allocating a connection parameter to each user terminal (14) based upon accessing a plurality of communication system parameters.

Abstract: The present invention provides a highly accurate synchronization method for a satellite communication system (100). The system maintains a downlink symbol counter at an earth terminal and determines a downlink symbol count representative of the time of arrival of a burst transmitted from the earth terminal to a satellite (106, 206). The earth terminal adjusts the downlink symbol counter to correspond to the downlink symbol count (136, 220) upon arrival of a predetermined reference point in a downlink frame. A timing error may initially be determined by launching an entry order wire from the earth terminal to the satellite (116). The timing error may be transmitted to the earth terminal using a correction code which indicates the transmission is early, late, absent, or no change is required (134, 218). The terminal may make additional periodic timing adjustments based on the length of the propagation path between the earth terminal and the satellite (108, 208).

Abstract: A method and apparatus for mitigation of false co-channel uplink reception, also known as show-thru, in an uplink A due to an uplink B at a satellite receiver. The method includes storing multiple scrambling sequences associated with respective individual uplinks, including a scrambling sequence A, receiving uplink A signals at an uplink A receiver, applying scrambling sequence A to the uplink A signals to generate descrambled A data, and then decoding the descrambled A data. The decoding step includes the generation of a decoder failure signal in the event that decoding is unsuccessful, and the method discards the descrambled A data if the decoder failure signal is asserted. Therefore, any show-thru data derived from uplink B will be discarded in the uplink A receiver, and vice versa. The step of applying the scrambling sequence may be effected using an exclusive-or operation.

Abstract: A downlink orderwire integrator (63) and separator (81) for use in a processing satellite (12) and a user terminal (14) in a satellite based communications system (10) is provided having a formatter (64), a cell switch (72) and a cell sieve (80). The formatter (64) generates orderwire cells (54) with each orderwire cell (54) having a header (60) and a body (62). The cell switch (72) receives the orderwire cells (54) from the formatter (64) and traffic cells (56) from at least one uplink (16) and arranges the orderwire cells (54) and the traffic cells (52) in at least one frame (48) to transmit on at least one downlink (18). The frame (48) includes a fixed custom frame portion (42) and a fixed traffic portion (50) that contains both the traffic cells (52) and the orderwire cells (54).

Abstract: An apparatus (100), and method, for calibrating gain in satellite uplink receiver electronics includes an uplink receiver, a measurement processor, and an attenuator (106). The measurement processor receives the uplink signal from the uplink receiver and includes circuitry to sample (118) the uplink signals during a blanking interval and outputs a gain calibration signal. The sampling circuitry (118) may sample uplink signals periodically or responsive to extreme changes in conditions, and may sample the uplink signal multiple times during a blanking interval to output a multiple measurement sample. The measurement processor may include averaging circuitry (124) to produce a sample average. The method and apparatus (200) may both be used with TDMA systems.

Abstract: An initial entry processor (40) for use in a processing satellite (12) in a satellite based communications system (10) is provided having a buffer (62), a detection and timing circuit (64) and an identity circuit (66). The buffer (62) stores an initial entry burst (54) transmitted from at least one terrestrial terminal (14) to the processing satellite (12). The detection and timing circuit (64) detects the initial entry burst (54) and determines a time of arrival of the initial entry burst (54) relative to an initial entry burst slot (52). The identity circuit (66) determines an identity of the terrestrial terminal (14) that transmitted the initial entry burst (54) such that the time of arrival is used by the identified terrestrial terminal (14) during subsequent communications with the processing satellite (12).

Abstract: An apparatus (100), and method, for calibrating gain in satellite uplink receiver electronics includes an uplink receiver, a measurement processor, and an attenuator (106). The measurement processor receives the uplink signal from the uplink receiver and includes circuitry to sample (118) the uplink signals during a blanking interval and outputs a gain calibration signal. The sampling circuitry (118) may sample uplink signals periodically or responsive to extreme changes in conditions, and may sample the uplink signal multiple times during a blanking interval to output a multiple measurement sample. The measurement processor may include averaging circuitry (124) to produce a sample average. The method and apparatus (200) may both be used with TDMA systems.

Abstract: The invention is a receiver and a method of receiving data having a preferred application in a satellite. A receiver in accordance with the invention includes at least one memory (118, 120), each memory including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal and outputs the stored data samples from a plurality of channels in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and an outer decoder (102), responsive to data blocks with each data block containing at least one data group, which decodes the data blocks and outputs decoded data blocks.

Abstract: Communication satellite downlink transmitting and reception techniques includes circuitry which groups a predetermined number of data cells with a predetermined error correction code to generate frame bodies. The circuitry also groups the frame bodies with header symbols and trailer symbols to generate data frames. One or more modulators enable the placement of the modulated data frames into a plurality of frequency bands having a predetermined frequency range and a predetermined transmission rate. One or more antennas transmit the modulated data frames over one or more beams with different forms of polarization to other antennas. A demodulator is connected to demodulate the radio carrier signals and the beams into data frames from a plurality of frequency bands. Decoders are connected to decode the frame bodies with header symbols and with trailer symbols from the data frames and to decode four data cells as a group by using a predetermined error correction code.

Abstract: Uplink transmission and reception techniques for a processing satellite including one or more earth terminals 400 connected to receive ATM data cells. One or more encoders 418 are connected to coordinate four data cells with an error correction code to generate data bursts and to coordinate the data bursts with synchronizing bursts to generate data frames. One or more modulators 420 are connected to modulate the data frames by frequency division multiple access modulation to enable placement of the modulated data frames into a plurality of channels. One or more antennas 406 transmit the modulated data frames to a satellite 100 over 48 beams with various forms of polarization. In satellite 100, a receiving multibeam antenna and feed 106 responds to one or more beams of radiocarrier signals having one or more forms of polarization. One or more demodulators 138 demodulate the radio carrier signals into data frames from various channels including a plurality of channel types.

Abstract: In a cellular satellite system such as Astrolink, where same frequency, same polarization (same “color”) signals are used in multiple ground cells, there exists the possibility of interference and false reception of uplink Synchronization Bursts (SB) in systems employing TDMA access of the frequency in question. In such systems, a SB transmitted from one terminal may be received in more than one satellite beam. The reception of the signal from a terminal in an undesired beam (330) is erroneous and may adversely impact the time synchronization (360) of the desired terminal. For example, a system may employ Maximal Length (ML) Pseudo-Noise (PN) sequences (410) for its SBs wherein every beam may use the same sequence. To minimize false reception, the ML PN sequences (410) of each SB may be cyclicly shifted a different amount for each beam to generate sequences (410, 420) having low corsscorrelation with each other.

Abstract: An uplink demodulator system (44) for use in a processing satellite (12) in a satellite based communications system (10) is provided with a first multiplexer (62), a second multiplexer (82), a multichannel preamble processor (66), and a multichannel phase tracker (68). The first multiplexer (62) is operable to receive channelized data from a plurality of channelization modes at a plurality of inputs and operable to route the channelized data to a first output. The multichannel preamble processor (66) is operable to determine a phase estimate for each channel of the channelized data. The multichannel phase tracker (68) is operable to receive the phase estimates from the multichannel preamble processor (66) and operable to track a phase for each channel of said channelized data to phase align each channel of said channelized data to corresponding uplink signals.

Abstract: A synchronization burst processor (56) used in a processing satellite (12) in a satellite based communications system (10) is provided with a sync burst memory (72), a first double correlator (74), a second double correlator (76) and a modulus module (78). The sync burst memory (72) stores at least one sync burst (52) transmitted from a terrestrial terminal (14) to the processing satellite (12) where the sync burst (52) is formed from a quadrature pair sample set {p, q}. The first double correlator (74) performs an early correlation and a late correlation of the p samples relative to a sync burst slot (50) to generate an early correlation Pe and a late correlation Pl. The second double correlator (76) performs an early correlation and a late correlation of the q samples relative to the sync burst slot (50) to generate an early correlation Qe and a late correlation Ql.

Abstract: A method and system for controlling uplink power in a satellite communication system using error leveling is provided. The uplink power control system for a satellite communication system of a preferred embodiment of the present invention comprises a communication satellite (101) and at least one UET (105). The communication satellite (101) includes an error detector (211) and a comparator (215). The UET (105) includes a receiver (206) for receiving an error indicator signal from the comparator (215), and a power profile processor (216) for controlling the transmit power level of the particular chanslot being used by the UET in response to the error indicator.

Abstract: The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14); a demultiplexer (16), coupled to the analog to digital converter, a window presum (102) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a cyclic shift (24′), coupled to I output groups of data words.

Abstract: The invention is an apparatus and process for performing a discrete Fourier transform and a digital channelizer which divides an input bandwidth into at least some of N channels. An apparatus for performing a discrete Fourier transform in accordance with the invention includes at least one discrete Fourier transform computation stage (304, 305′, 402, 410, 412, 414, 419), the at least one discrete Fourier transform computation stage having N inputs representing preselected frequency bands with each input containing an input signal containing real data and P actual outputs each containing an output signal, P being less than N, at least one of the P actual output signals containing a conjugate of one of the N input frequency bands; and a processing device (602, 702), coupled to at least one P actual output containing a signal which is a conjugate, which processes the conjugate as representative of one of the N input frequency bands.

Abstract: The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102); a cyclic shift (24′), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26′) coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.

Abstract: A digital channelizer and a process for dividing input bandwidth into at least some of N channels are disclosed. The digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14), a demodulator (16) coupled to the analog to digital converter, a window presum (102) coupled to the parallel streams of data words and a discrete Fourier transform apparatus (26′), coupled to the N outputs of the window presum, having N inputs and which performs a discrete Fourier transform on the N inputs to output at least some of the N channels.

Abstract: A wideband digital tuner (14′) has an analog front-end section (10), a high speed analog-to-digital converter (12), demultiplexer (13) and a plurality of filters (341-342) arranged in a parallel input architecture to process wideband digital data received at extremely high sampling rates, such as at 2 Gsps (giga-samples per second). The tuner greatly attenuates an undesired spectral half of the wide bandwidth digital spectrum of the incoming digital signal using a complex band-pass filter, such as a Hilbert Transform filter. The tuner places the remaining half of the wide bandwidth digital spectrum of the incoming digital signal at complex baseband and down samples by 2. The architecture of the tuner can be partitioned into two separate halves which are hardware copies of each other.