Patents by Inventor Gregory S. Clemons
Gregory S. Clemons has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10794840Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for package inspection. In some embodiments, the apparatus may include a light source to selectively project a first light defined by a first wavelength range to a surface of a package under inspection; an optical filter to selectively transmit, within a second wavelength range, a second light emitted by the surface of the package in response to the projection of the first light to the surface; a camera to generate one or more images of the surface, defined by the second light; and a controller coupled with the light source, optical filter, and camera, to process the one or more images, to detect a presence of a material of interest on the surface of the package, based at least in part on the first and second wavelength ranges. Other embodiments may be described and/or claimed.Type: GrantFiled: March 17, 2017Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Liang Zhang, Jianyong Mo, Darren A. Vance, Di Xu, Gregory S. Clemons, Robert F. Wiedmaier
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Publication number: 20190339212Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for package inspection. In some embodiments, the apparatus may include a light source to selectively project a first light defined by a first wavelength range to a surface of a package under inspection; an optical filter to selectively transmit, within a second wavelength range, a second light emitted by the surface of the package in response to the projection of the first light to the surface; a camera to generate one or more images of the surface, defined by the second light; and a controller coupled with the light source, optical filter, and camera, to process the one or more images, to detect a presence of a material of interest on the surface of the package, based at least in part on the first and second wavelength ranges. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 17, 2017Publication date: November 7, 2019Inventors: Liang ZHANG, Jianyong MO, Darren A. VANCE, Di XU, Gregory S. CLEMONS, Robert F. WIEDMAIER
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Patent number: 10468367Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: GrantFiled: January 30, 2018Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Publication number: 20180151529Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: ApplicationFiled: January 30, 2018Publication date: May 31, 2018Applicant: INTEL CORPORATIONInventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Patent number: 9530747Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: GrantFiled: March 10, 2015Date of Patent: December 27, 2016Assignee: Intel CorporationInventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Publication number: 20160148892Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: ApplicationFiled: January 28, 2016Publication date: May 26, 2016Applicant: Intel CorporationInventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Publication number: 20150187727Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Applicant: INTEL CORPORATIONInventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Patent number: 9006890Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: GrantFiled: January 14, 2013Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Chuan Hu, Shawna M Liff, Gregory S Clemons
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Patent number: 8936967Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: GrantFiled: March 23, 2011Date of Patent: January 20, 2015Assignee: Intel CorporationInventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Publication number: 20130128484Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: ApplicationFiled: January 14, 2013Publication date: May 23, 2013Inventors: Chaun Hu, Shawna M. Liff, Gregory S. Clemons
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Publication number: 20120241965Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Inventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
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Patent number: 7584536Abstract: The specification discloses an apparatus comprising an alignment plate having a plurality of depressions therein, each depression being sized to receive a packaging cap therein and to prevent its movement, and a force applicator to apply a force to press the packaging caps and a substrate firmly together. Also disclosed is a process comprising inserting a plurality of packaging caps in a plurality of depressions on an alignment plate, each depression being sized to receive a packaging cap and prevent its movement, aligning the plurality of packaging caps with individual devices on a substrate, placing the substrate in contact with the packaging caps, and applying a force to press the caps against the substrate. Other embodiments are disclosed and claimed.Type: GrantFiled: July 13, 2007Date of Patent: September 8, 2009Assignee: Intel CorporationInventors: Gregory S. Clemons, Mitesh C. Patel
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Patent number: 7297369Abstract: A process is disclosed for imprinting microgrooves in a polymer layer to create an alignment layer for a liquid crystal display. In one embodiment, the process comprises providing a transparent substrate having a polymer film applied on one side thereof, providing a tool having a contact surface, the contact surface having a plurality of microgrooves formed thereon, and pressing the contact surface against the polymer film. Additional embodiments are also disclosed and claimed.Type: GrantFiled: March 31, 2004Date of Patent: November 20, 2007Assignee: Intel CorporationInventor: Gregory S. Clemons
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Patent number: 7275312Abstract: The specification discloses an apparatus comprising an alignment plate having a plurality of depressions therein, each depression being sized to receive a packaging cap therein and to prevent its movement, and a force applicator to apply a force to press the packaging caps and a substrate firmly together. Also disclosed is a process comprising inserting a plurality of packaging caps in a plurality of depressions on an alignment plate, each depression being sized to receive a packaging cap and prevent its movement, aligning the plurality of packaging caps with individual devices on a substrate, placing the substrate in contact with the packaging caps, and applying a force to press the caps against the substrate. Other embodiments are disclosed and claimed.Type: GrantFiled: June 30, 2003Date of Patent: October 2, 2007Assignee: Intel CorporationInventors: Gregory S. Clemons, Mitesh C. Patel
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Patent number: 6892927Abstract: A method of bonding a wire to a bond pad on an electronic or photonic device is provided. A section of the wire is held within a bond head of the wirebonding apparatus. A laser beam is directed onto the bond pad. Energy of the laser beam heats the bond pad to the temperature that is higher than the temperature of the device. The bond head is subsequently moved toward the device to bring a portion of the wire into contact with the bond pad. Ultrasonic energy is provided to an interface between the portion of the wire and the bond pad.Type: GrantFiled: April 24, 2003Date of Patent: May 17, 2005Assignee: Intel CorporationInventors: Christopher L. Rumer, Gregory S. Clemons
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Patent number: 6867124Abstract: A system may direct first energy to only a first interconnect element, the first interconnect element contacting a first conductive contact of a first device and a second conductive contact of a second device. A first electrical connection may be formed between the first conductive contact and the second conductive contact based at least in part on the first energy. Further, second energy may be directed to only a second interconnect element, the second interconnect element contacting a third conductive contact of the first device and a fourth conductive contact of the second device. A second electrical connection may be formed between the third conductive contact and the fourth conductive contact based at least in part on the second energy.Type: GrantFiled: December 4, 2003Date of Patent: March 15, 2005Assignee: Intel CorporationInventors: Gregory S. Clemons, Christopher L. Rumer
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Publication number: 20040261262Abstract: The specification discloses an apparatus comprising an alignment plate having a plurality of depressions therein, each depression being sized to receive a packaging cap therein and to prevent its movement, and a force applicator to apply a force to press the packaging caps and a substrate firmly together. Also disclosed is a process comprising inserting a plurality of packaging caps in a plurality of depressions on an alignment plate, each depression being sized to receive a packaging cap and prevent its movement, aligning the plurality of packaging caps with individual devices on a substrate, placing the substrate in contact with the packaging caps, and applying a force to press the caps against the substrate. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Gregory S. Clemons, Mitesh C. Patel
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Publication number: 20040211761Abstract: A method of bonding a wire to a bond pad on an electronic or photonic device is provided. A section of the wire is held within a bond head of the wirebonding apparatus. A laser beam is directed onto the bond pad. Energy of the laser beam heats the bond pad to the temperature that is higher than the temperature of the device. The bond head is subsequently moved toward the device to bring a portion of the wire into contact with the bond pad. Ultrasonic energy is provided to an interface between the portion of the wire and the bond pad.Type: ApplicationFiled: April 24, 2003Publication date: October 28, 2004Inventors: Christopher L. Rumer, Gregory S. Clemons