Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Abstract: A digital signal processor with an embedded error correcting coprocessor (ECCP) is disclosed. The ECCP provides soft symbol Viterbi decoded outputs which have the absolute value of the accumulated cost difference of competing states concatenated with the traceback bit or most significant bit of the next state.

Abstract: A digital communication system including Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. The trellis of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. A second traceback is also initiated at the first symbol instant and traces a path back through the trellis a second predetermined number symbol instants to determine a second decoded symbol. The first traceback length may be greater than or less than the second traceback length. In another embodiment of the invention several tracebacks can be executed having a fixed traceback length, followed by other tracebacks having incrementally different traceback lengths.

Abstract: A communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A matrix of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. The length of the traceback is changed and another traceback is executed. This process is repeated until all remaining final decoded symbols are decoded. In an alternate embodiment, the traceback length is repreatedly decremented by one less than the constraint length, with each traceback obtaining multiple decoded symbols.

Abstract: Convolutionally encoded information subjected to channel intersymbol interference is decoded by calculating the minimum cost path through a trellis. The trellis terminates in known states. Exploiting the open architecture of the coprocessor, the minimum cost state is checked to ascertain if it is the known, that is, correct state and if it is not, the possible known states are searched by the DSP inside the ECCP active register and the state with the lowest cost amont the possible states is selected.

Abstract: A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over-writing the traceback length register.

Abstract: There is disclosed a soft symbol for use in a decoding process generated from a binary representation of a branch metric. When a hard decision bit is a zero, a preselected number of bits of a binary representation of the branch metric are concatenated with a hard decision bit to form the soft symbol. When the hard decision bit is a one, the ones complement of the preselected number of bits of the binary representation of the branch metric are concatenated with the hard decision bit to form the soft symbol. The concatenation function can be achieved using an exclusive OR function with the preselected bits of the binary representation of the branch metric and the hard decision bit to form the soft symbol. The hard decision bit may be selectable from more than one source.

Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Abstract: A signal processor with an embedded Viterbi co-processor is disclosed. The Viterbi branch metric unit contains embedded metric units which calculate either Euclidean or Manhattan metrics for MLSE or deconvolution operations.