Abstract: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.

Abstract: Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a method for implementing a logic gate comprises: providing a first layer of approximately parallel nanowires; interconnecting the first layer of approximately parallel nanowires with a second layer of approximately parallel nanowires through configurable, tunneling resistor junctions; selecting nanowires from among the first and second layer of nanowires to carry input and output electrical signals representing logical values; applying electrical signals representing input logical values to the input nanowires; and detecting an electrical signal representing an output logical value on the output nanowires.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer.

Abstract: Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a nanowire crossbar comprises two or more layers of approximately parallel nanowires, and a number of configurable, tunneling resistor junctions that each interconnects a nanowire in a first layer of approximately parallel nanowires with a nanowire in a second layer of approximately parallel nanowires.

Abstract: One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.

Abstract: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer.

Abstract: A power hand tool can include a generally longitudinal housing having a first end and a second end. An indicator can be disposed on the housing. A first and a second jaw member can be arranged at the first end wherein one of the first and second jaw members can rotate relative to the other jaw member. A motor assembly can be disposed in the housing and include an output member arranged at the second end. A sensor can be arranged at the second end and configured to sense an electrical field in proximity thereof. The sensor can generate a signal in response to a sensed electrical field. A controller can receive the sensor signal from the sensor assembly and control operation of the indicator in response thereto.

Abstract: A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit and to the programmable logic circuit. The instruction processing circuit executes instructions of a native instruction set, and the programmable logic is configured to dynamically translate input instructions to translated instructions of the native instruction set. The translated instructions are stored in a translation cache in the memory arrangement, and the translation cache is managed by the programmable logic. The programmable logic then provides the translated instructions to the instruction processing circuit for execution.

Abstract: Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.

Abstract: In one embodiment of the present invention, a nanoscale latch is implemented by interconnecting an enable line, two control lines, and a pull-down line, when needed, to a signal line carrying encoded binary values to be latched and subsequently output. The enable line is interconnected with the signal line through a field-effect-transistor-like nanoscale junction. Both control lines are interconnected with the signal line through asymmetric-switch nanoscale junctions of like polarities. The pull-down line, when needed, is interconnected with the signal line through a resistive nanoscale junction. Inputting a sequence of signals to the enable and control lines allows a value input from the signal line to be stored and subsequently output to the signal line. In various additional embodiments, an array of nanoscale latches can be implemented by overlaying enable and control lines, and a pull-down line when needed, over a set of parallel nanowires.

Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.

Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.

Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.

Abstract: Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.

Abstract: A lock set installation apparatus has a pair of hole saw guides which locate a hole to receive door operating members of a lock set. Each hole saw guide has at least one rail member which oppose one another. A lock bolt hole mechanism is movable and coupled with the rails. The lock bolt hole mechanism centers the lock bolt hole onto the door. A locking mechanism locks the hole saw guides with respect to one another to enable cutting of the door.

Abstract: Various embodiments of the present invention are directed to antisymmetric nanowire-crossbar-circuit designs. Antisymmetric nanowire crossbars are composed, in certain embodiments of the present invention, of two or more microregions that receive input signals and two or more microregions that send output signals. Antisymmetric nanowire crossbars may include a nanowire-crossbar network having signal paths that carry signals between one or more of the microregions. The nanowire-crossbar network may also carry signals between external electronic devices and one or more of the microregions. Antisymmetric nanowire crossbars may additionally include two or more structures that supply voltage and ground.