Patents by Inventor Gregory S. Vasche

Gregory S. Vasche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5793155
    Abstract: An improved vacuum microelectronic device comprised of a first polysilicon layer having hornlike protrusions forming the emitter of the device, a first insulating layer separating the first polysilicon layer from a second polysilicon layer forming the grid of the device; a second insulating layer separating the second and third polysilicon layers. A portion of the first insulating layer, the second polysilicon layer, and second insulating layers are removed to form a grid aperture region positioned directly above the hornlike protrusion of the emitter. A cavity exists between the grid aperture region and a third polysilicon layer. The cavity is evacuated to form the vacuum region of the device.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: August 11, 1998
    Inventor: Gregory S. Vasche
  • Patent number: 5409568
    Abstract: An improved vacuum microelectronic device comprised of a first polysilicon layer-having hornlike protrusions forming the emitter of the device, a first insulating layer separating the first polysilicon layer from a second polysilicon layer forming the grid of the device; a second insulating layer separating the second and third polysilicon layers. A portion of the first insulating layer, the second polysilicon layer, and second insulating layers are removed to form a grid aperture region positioned directly above the hornlike protrusion of the emitter. A cavity exists between the grid aperture region and a third polysilicon layer. The cavity is evacuated to form the vacuum region of the device.
    Type: Grant
    Filed: August 4, 1992
    Date of Patent: April 25, 1995
    Inventor: Gregory S. Vasche
  • Patent number: 5219774
    Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: June 15, 1993
    Assignee: Xicor, Inc.
    Inventor: Gregory S. Vasche