Abstract: Semiconductor device and circuits and methods of fabrication which provides multilevel interconnections with grown diamond insulation films and second level resistors in the diamond insulation. The diamond provides both good electrical insulation and good thermal conductivity. The methods also provide capacitors with second level diamond dielectrics.

Abstract: A semiconductor-on-diamond structure has a free-standing layer of diamond material that is thick enough to provide integrity for the integrated circuit and to insulate the circuit. The structure has a layer of diamond material 12 on a layer of silicon nitride 62. A device layer of semiconductor material 30 is positioned over the silicon nitride layer.

Abstract: An integrated circuit structure containing dielectrically isolated islands having heat dissipation paths of enhanced thermal conductivity. A semiconductor structure comprises a first layer of crystalline material with a layer comprising polycrystalline diamond formed over the first layer. A layer of polycrystalline silicon is formed over the diamond containing layer and a layer of monocrystalline material is formed over the polycrystalline silicon.

Abstract: Silicon on diamond die 5 are separated by patterning the diamond layer 3 and sawing the silicon layer 4. The diamond layer 3 is patterned by known techniques including laser ablation or using a silicon dioxide mask to resist deposition of diamond material. Patterning may take place after formation of microelectronic devices in dies in the silicon layer, after a device water is bonded to a diamond layer but before formation of the devices, prior to joining the device wafer to the diamond layer.

Abstract: A semiconductor-on-insulator structure incorporating a layer of diamond material and method for preparing such. The structure comprises a layer containing diamond material and having a first surface. A layer of silicon nitride is formed on the first surface and a layer of semiconductor material is positioned over the silicon nitride layer. In one embodiment of the method there is provided a removable deposition surface. A layer of crystalline diamond material is formed on the deposition surface. A first surface of the diamond material is separated from the deposition surface. The structure is useful for formation of integrated circuits thereon.

Abstract: An ion-implanted JFET has a channel barrier region at the top gate surface self-aligned to the source and drain, thereby maintaining sufficient separation between the channel barrier and the source and drain for attaining a high source/drain breakdown voltage. After a top gate and an underlying channel layer are ion-implanted through a thin oxide layer, a first photoresist layer is formed and patterned to expose surface portions of the thin oxide layer where source, drain and channel barrier regions are to be formed. Through these apertures in the first photoresist mask, shallow high impurity concentration surface region are ion-implanted. A second photoresist layer is formed on the first photoresist layer, and patterned to completely expose the first and second apertures in the first photoresist layer and to remove material of the second photoresistor layer down to the surface of the the oxide layer, while masking the barrier region.

Abstract: Radiation insensitivity and breakdown voltage characteristics of a dual region top gate JFET are improved by a top gate structure in which the entirety of the lower concentration region of the top gate is separated from the oxide/silicon interface by the top surface high impurity concentration region. The dual region top gate extends from the substrate/insulator interface to a channel region beneath the top surface of the JFET substrate and extends laterally to bridge the source and drain regions. The lateral extent of the dual region top gate may be deliminated by barrier regions, respectively separating the top gate regions from the source and drain regions. The barrier regions extend from the substrate/oxide interface to the channel and may comprise dielectric material or a combination of dielectric material and doped semiconductor material.

Abstract: A polycrystalline silicon layer forms an Ohmic contact to a group III-arsenide compound semiconductor substrate by heating the substrate. The polysilicon contact out-diffuses silicon into the substrate to form an N++ region.

Abstract: Radiation insensitivity and breakdown voltage characteristics of a dual region top gate JFET are improved by a top gate structure in which the entirety of the lower concentration region of the top gate is separated from the oxide/silicon interface by the top surface high impurity concentration region. The dual region top gate extends from the substrate/insulator interface to a channel region beneath the top surface of the JFET substrate and extends laterally to bridge the source and drain regions. The lateral extent of the dual region top gate may be delimited by barrier regions, respectively separating the top gate regions from the source and drain regions. The barrier regions extend from the substrate/oxide interface to the channel and may comprise dielectric material or a combination of dielectric material and doped semiconductor material.

Abstract: A method of fabricating I.sup.2 JFETs including separately and in combination out-diffusion of impurities from doped source and drain contact material to product self-aligned source and drains; using the source and drain contacts as mask to form a self-aligned top gate spaced from the source and drain; and dual ion implantation of the channel for increasing radiation hardness.

Abstract: The gate-drain breakdown voltage of an ion-implanted JFET is effectively increased by forming the top gate region through two sequential implantation steps to result in respective pockets of different impurity concentration. The deeper pocket (defining the top gate-drain PN junction) has a low impurity concentration profile thereby increasing the breakdown voltage of the gate-drain PN junction, while a second higher impurity concentration implant, which forms a pocket in the first implanted pocket of the top gate, provides the necessary charge carrier concentration to prevent the top gate from becoming fully depleted when the device is biased near pinch-off.