Abstract: A scanned beam display is operable to compensate for variations in apparent pixel brightness arising from variations in beam scanning velocity and/or pixel dwell times. A compensation circuit modifies pixel values according to their scanning velocity and/or dwell time.

Abstract: A scanning control circuit generates a clock signal corresponding to an expected scan timing of a resonant scanner. In one approach, the control circuit uses a pair of direct digital synthesis (DDS) integrated circuits. A first DDS chip provides a system clock that is synchronized to the monitored period of the scanner. A second DDS chip generates a frequency chirped signal that has a frequency profile corresponding to a desired pixel clock timing. To control phase precisely, four complementary clock signals are weighted and mixed at light source drivers to produce relative phase shifts for different light sources.

Abstract: A scanning control circuit generates a clock signal corresponding to an expected scan timing of a resonant scanner. In one approach, the control circuit uses a pair of direct digital synthesis (DDS) integrated circuits. A first DDS chip provides a system clock that is synchronized to the monitored period of the scanner. A second DDS chip generates a frequency chirped signal that has a frequency profile corresponding to a desired pixel clock timing. To control phase precisely, four complementary clock signals are weighted and mixed at light source drivers to produce relative phase shifts for different light sources.