Abstract: An electromagnetic radiation sensor that exhibits improved performance by virtue of an ability to tune its sensitivity is disclosed. The electromagnetic radiation sensor incorporates thermal actuators that act in opposition to one another, but which have a slight difference in responsivity. A temperature controller is used to tune the sensitivity of the electromagnetic radiation sensor by controlling the temperature of the substrate on which the sensor is formed.

Abstract: A radiation sensor array that exhibits improved fill factor is disclosed. The radiation sensor array incorporates sensors having support arms that are nested in vertical fashion with the support arms of neighboring sensors. This vertically-nested structure enables the radiation-sensing portions of the sensors to be more closely-packed.

Abstract: An electromagnetic radiation sensor that exhibits improved performance by virtue of an ability to tune its sensitivity is disclosed. The electromagnetic radiation sensor incorporates thermal actuators that act in opposition to one another, but which have a slight difference in responsivity. A temperature controller is used to tune the sensitivity of the electromagnetic radiation sensor by controlling the temperature of the substrate on which the sensor is formed.

Abstract: A radiation sensor array that exhibits improved fill factor is disclosed. The radiation sensor array incorporates sensors having support arms that are nested in vertical fashion with the support arms of neighboring sensors. This vertically-nested structure enables the radiation-sensing portions of the sensors to be more closely-packed.

Abstract: A thermal bimorph that exhibits improved layer adhesion and an enhanced bending response is disclosed. The thermal bimorph incorporates corrugations that extend fully through the bimorph to its two major surfaces. In some embodiments, the thermal bimorph is asymmetrically corrugated.

Abstract: A method of forming a side access layer on a semiconductor chip, or especially a stack of semiconductor chips, is provided. A region of protective insulating material and one or more conductive pads are formed above a major surface of each chip substrate. Each conductive pad is located at least a certain height above the major surface of the substrate and at least a certain distance away from a side surface of the chip, with the region of protective material generally extending between each conductive pad and the major surface of the substrate. The insulating material thereby protects each conductive pad during subsequent etching of the side surface of each chip substrate. The edge of each conductive pad is then exposed, preferably by planarizing the side surface of the chip or stack. Also, a side interconnect layer may be formed on the side surface of the chip or stack to provide an electrical connection to each conductive pad.