Patents by Inventor Gregory Snider

Gregory Snider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327496
    Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.
    Type: Application
    Filed: February 19, 2021
    Publication date: October 21, 2021
    Inventors: Gregory Snider, Rene Celis-Cordova, Alexei Orlov, Tian Lu, Jason M. Kulick
  • Publication number: 20170098716
    Abstract: A two-dimensional (2D) heterojunction interlayer tunneling field effect transistor (Thin-TFET) allows for particle tunneling in a vertical stack comprising monolayers of two-dimensional semiconductors separated by an interlayer. In some examples, the two 2D materials may be misaligned so as to influence the magnitude of the tunneling current, but have a modest impact on gate voltage dependence. The Thin-TFET can achieve very steep subthreshold swing, whose lower limit is ultimately set by the band tails in the energy gaps of the 2D materials produced by energy broadening. These qualities in turn make the Thin-TFET an ideal low voltage, low energy solid state electronic switch.
    Type: Application
    Filed: February 23, 2015
    Publication date: April 6, 2017
    Inventors: Mingda Li, David Esseni, Gregory Snider, Debdeep Jena, Huili Grace Xing
  • Patent number: 7900187
    Abstract: Software that modifies the source code for readily available software tasks—typically applications and hardware drivers—so that a small, fast, reliable operating system can be synthesized to control execution of these readily available software tasks.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: March 1, 2011
    Assignee: Robert Zeidman
    Inventors: Robert M. Zeidman, Gregory Snider
  • Publication number: 20070238291
    Abstract: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer.
    Type: Application
    Filed: October 21, 2005
    Publication date: October 11, 2007
    Inventors: Gregory Snider, Phillip Kuekes
  • Publication number: 20070205483
    Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.
    Type: Application
    Filed: January 31, 2007
    Publication date: September 6, 2007
    Inventors: R. Williams, Gregory Snider, Duncan Stewart
  • Publication number: 20070189868
    Abstract: A lock set installation apparatus has a pair of hole saw guides which locate a hole to receive door operating members of a lock set. Each hole saw guide has at least one rail member which oppose one another. A lock bolt hole mechanism is movable and coupled with the rails. The lock bolt hole mechanism centers the lock bolt hole onto the door. A locking mechanism locks the hole saw guides with respect to one another to enable cutting of the door.
    Type: Application
    Filed: April 17, 2007
    Publication date: August 16, 2007
    Inventors: Gregory Snider, James Pangerc
  • Publication number: 20070176630
    Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.
    Type: Application
    Filed: January 31, 2006
    Publication date: August 2, 2007
    Inventors: Gregory Snider, Philip Kuekes
  • Publication number: 20070176801
    Abstract: Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 2, 2007
    Inventors: Warren Robinett, Gregory Snider, Duncan Stewart, Joseph Straznicky
  • Publication number: 20070176168
    Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 2, 2007
    Inventors: Gregory Snider, R. Williams
  • Publication number: 20070172235
    Abstract: Various embodiments of the present invention are directed to photonic-interconnection-based compute clusters that provide high-speed, high-bandwidth interconnections between compute cluster nodes. In one embodiment of the present invention, the compute cluster includes a photonic interconnection having one or more optical transmission paths for transmitting independent frequency channels within an optical signal to each node in a set of nodes. The compute cluster includes one or more photonic-interconnection-based writers, each writer associated with a particular node, and each writer encoding information generated by the node into one of the independent frequency channels. A switch fabric directs the information encoded in the independent frequency channels to one or more nodes in the compute cluster.
    Type: Application
    Filed: January 23, 2006
    Publication date: July 26, 2007
    Inventors: Gregory Snider, Raymond Beausoleil
  • Publication number: 20070131306
    Abstract: A support stand for a tool such as a miter saw is disclosed. The stand includes legs, a beam supported by the legs, and a pair of tool support platforms that may be connected to the tool. The tool support platforms are configured to slide along the beam; moreover, they can be removed from the beam and placed on a supporting surface. Each platform may include a receptacle that engages a clip fastened to the beam. The clip engages the platform to prevent its movement along the beam. Each platform also includes a series of slots through which fasteners are inserted. The slots allow the fasteners to be repositioned so they can be aligned with the specific connection points on a variety of different tools (including tools of different manufacturers).
    Type: Application
    Filed: December 9, 2005
    Publication date: June 14, 2007
    Inventor: Gregory Snider
  • Publication number: 20070109014
    Abstract: One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions.
    Type: Application
    Filed: July 27, 2005
    Publication date: May 17, 2007
    Inventors: Gregory Snider, Philip Kuekes, Duncan Stewart
  • Publication number: 20070101308
    Abstract: Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a nanowire crossbar comprises two or more layers of approximately parallel nanowires, and a number of configurable, tunneling resistor junctions that each interconnects a nanowire in a first layer of approximately parallel nanowires with a nanowire in a second layer of approximately parallel nanowires.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventor: Gregory Snider
  • Publication number: 20070094756
    Abstract: One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.
    Type: Application
    Filed: October 21, 2005
    Publication date: April 26, 2007
    Inventors: Gregory Snider, Philip Kuekes
  • Publication number: 20060268598
    Abstract: Various embodiments of the present invention are directed to a signal-storing nanowire-crossbar latch array. In one embodiment, the signal-storing nanowire-crossbar latch array is fabricated from three signal lines, including an enable line and two control lines, that cross and intersect with a number of signal wires. Signals are stored in the nanowire-crossbar latch array, and output from the nanowire-crossbar latch array, by applying an input signal to each signal wire and applying selected voltages and voltage pulses to the control lines. In alternate embodiments, a second enable line that crosses and interconnects with each signal wire is added to the nanowire-crossbar latch array.
    Type: Application
    Filed: May 24, 2005
    Publication date: November 30, 2006
    Inventor: Gregory Snider
  • Publication number: 20060266999
    Abstract: Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.
    Type: Application
    Filed: May 24, 2005
    Publication date: November 30, 2006
    Inventors: Gregory Snider, Philip Kuekes
  • Publication number: 20060250878
    Abstract: Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a minimal number of address lines needed for unique addressing in a deterministic, non-randomly fabricated multiplexer or demultiplexer are used. The number of address lines in excess of the minimal number of address lines needed for unique addressing in a deterministic multiplexer or demultiplexer are referred to as supplemental address lines.
    Type: Application
    Filed: May 6, 2005
    Publication date: November 9, 2006
    Inventor: Gregory Snider
  • Publication number: 20060253832
    Abstract: Software that modifies the source code for readily available software tasks—typically applications and hardware drivers—so that a small, fast, reliable operating system can be synthesized to control execution of these readily available software tasks.
    Type: Application
    Filed: April 25, 2006
    Publication date: November 9, 2006
    Inventors: Robert Zeidman, Gregory Snider
  • Publication number: 20060202358
    Abstract: Various embodiments of the present invention are directed to antisymmetric nanowire-crossbar-circuit designs. Antisymmetric nanowire crossbars are composed, in certain embodiments of the present invention, of two or more microregions that receive input signals and two or more microregions that send output signals. Antisymmetric nanowire crossbars may include a nanowire-crossbar network having signal paths that carry signals between one or more of the microregions. The nanowire-crossbar network may also carry signals between external electronic devices and one or more of the microregions. Antisymmetric nanowire crossbars may additionally include two or more structures that supply voltage and ground.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 14, 2006
    Inventor: Gregory Snider
  • Publication number: 20060190896
    Abstract: Various embodiments of the present invention provide methods for designing multilayer nanowire crossbars that are functionally equivalent to two-layer nanowire-crossbar designs. Given a two-layer nanowire-crossbar design having two or more columns of microregions, in certain embodiments, the method conceptually folds the two-layer nanowire crossbar between columns of microregions. The folded nanowires, located in the conceptually folded, two-layer nanowire-crossbar design, are collapsed into shorter length nanowires to give a multilayer nanowire-crossbar design that includes the same number of nanowire junctions as in the two-layer nanowire-crossbar design.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 24, 2006
    Inventor: Gregory Snider