Patents by Inventor Gregory Stecker

Gregory Stecker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160111705
    Abstract: An air cathode battery is provided with a slurry anode. An anode cavity is interposed between the air cathode interior surfaces, with an anode compartment occupying the anode cavity. The anode compartment has a first wall and a second wall, one or both capable of movement. An anode current collector pouch has walls adjacent to interior surfaces of the anode compartment. A zinc slurry occupies an expandable region in the anode compartment between the anode current collector pouch and the anode compartment wall interior surfaces. The anode current collector pouch first wall and second wall contract towards each other in response to expansion in the volume of zinc slurry. In one aspect, the anode compartment first and second walls expand away from each other in response to expansion in the volume of zinc oxide. A replenishable electrolyte source may be used to provide electrolyte to the anode cavity.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Hidayat Kisdarjono, Alexander Bauer, Gregory Stecker, Wei Pan
  • Publication number: 20160099674
    Abstract: A flat panel photovoltaic (PV) system is provided formed from a first sheet with rows of concentrated III-V photovoltaic (CPV) solar cells. An overlying second sheet is made up of rows of waveguides, where each waveguide is coupled to a corresponding CPV solar cell. A third sheet includes overlying one-piece linear lenses, each having a focal line coupled to the waveguides in a corresponding row. Optionally, a fourth sheet underlies the first sheet, which is a 1-sun solar panel including a plurality of silicon PV cells. In one variation adjacent rows of waveguides couple to the same row of CPV cells. In another variation, each waveguide in a row is optically coupled to waveguides in an adjacent row, which adjacent waveguides are then coupled to a corresponding row of CPV cells. A lens overlies each row of waveguides, with a focal line coupled to each waveguide in that row.
    Type: Application
    Filed: August 13, 2015
    Publication date: April 7, 2016
    Inventors: Wei Pan, Douglas Tweet, Brian Wheelwright, Gregory Stecker, David Evans, Hao-Chih Yuan
  • Publication number: 20070167008
    Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
    Type: Application
    Filed: March 14, 2007
    Publication date: July 19, 2007
    Inventors: Sheng Hsu, Fengyan Zhang, Gregory Stecker, Robert Barrowcliff
  • Publication number: 20060180817
    Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
    Type: Application
    Filed: February 17, 2005
    Publication date: August 17, 2006
    Inventors: Sheng Hsu, Fengyan Zhang, Gregory Stecker, Robert Barrowcliff
  • Publication number: 20060160304
    Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
    Type: Application
    Filed: January 19, 2005
    Publication date: July 20, 2006
    Inventors: Sheng Hsu, Fengyan Zhang, Gregory Stecker, Robert Barrowcliff
  • Publication number: 20060124926
    Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
    Type: Application
    Filed: January 26, 2006
    Publication date: June 15, 2006
    Inventors: Fengyan Zhang, Gregory Stecker, Robert Barrowcliff, Sheng Hsu
  • Publication number: 20060099758
    Abstract: A method is provided for forming iridium oxide (IrOx) nanotubes. The method comprises: providing a substrate; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; introducing oxygen as a precursor reaction gas; establishing a final pressure in the range of 1 to 50 Torr; establishing a substrate, or chamber temperature in the range of 200 to 500 degrees C.; and using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx hollow nanotubes from the substrate surface. Typically, the (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor is initially heated in an ampule to a first temperature in the range of 60 to 90 degrees C., and the first temperature is maintained in the transport line introducing the precursor. The precursor may be mixed with an inert carrier gas such as Ar, or the oxygen precursor reaction gas may be used as the carrier.
    Type: Application
    Filed: October 21, 2004
    Publication date: May 11, 2006
    Inventors: Fengyan Zhang, Robert Barrowcliff, Gregory Stecker, Sheng Hsu
  • Publication number: 20060088993
    Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
    Type: Application
    Filed: December 15, 2004
    Publication date: April 27, 2006
    Inventors: Fengyan Zhang, Gregory Stecker, Robert Barrowcliff, Sheng Hsu
  • Publication number: 20060071207
    Abstract: Zinc-oxide nanostructures are formed by forming a pattern on a surface of a substrate. A catalyst metal, such as nickel, is formed on the surface of the substrate. Growth of at least one zinc oxide nanostructure is induced on the catalyst metal substantially over the pattern on the surface of the substrate based on a vapor-liquid-solid technique. In one exemplary embodiment, inducing the growth of at least one zinc-oxide nanostructure induces growth of each zinc-oxide nanostructure substantially over a patterned polysilicon layer. In another exemplary embodiment, when growth of at least one zinc-oxide nanostructure is induced, each zinc-oxide nanostructure grows substantially over an etched silicon substrate layer.
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Inventors: John Conley, Lisa Stecker, Gregory Stecker
  • Publication number: 20050158994
    Abstract: A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Wei-Wei Zhuang, Lisa Stecker, Gregory Stecker, Sheng Hsu