Abstract: Piecewise smooth regularization of data is disclosed. One example is a system where input data is received, the input data being associated with a certainty function indicative of confidence of each data element in the input data. Guide data including information indicative of presumed piecewise smoothness of the input data is received. A joint edge-aware filter is applied, based on the guide data, to the input data to provide filtered data. The joint edge-aware filter is applied, based on the guide data, to the certainty function to provide filtered certainty. A normalized convolution algorithm is applied to the filtered data and the filtered certainty to provide output data indicative of a piecewise smooth regularization of the input data.

Abstract: Piecewise smooth regularization of data is disclosed. One example is a system where input data is received, the input data being associated with a certainty function indicative of confidence of each data element in the input data. Guide data including information indicative of presumed piecewise smoothness of the input data is received. A joint edge-aware filter is applied, based on the guide data, to the input data to provide filtered data. The joint edge-aware filter is applied, based on the guide data, to the certainty function to provide filtered certainty. A normalized convolution algorithm is applied to the filtered data and the filtered certainty to provide output data indicative of a piecewise smooth regularization of the input data.

Abstract: Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse. The method includes loading the N-bit codeword into a circular shift register and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse.

Abstract: In one implementation, a compilation system identifies a plurality of objects within a description of an application, determines a plurality of state paths among the objects, and generates a plurality of executable objects that are independently executable and are each associated with a data structure representing a state of that executable object. Each state path is derived from an operation included in the description of the application on an object from the objects for which another object from the objects is an operand. Each executable object includes instructions that when executed at a host cause the host to perform an operation associated with that executable object and provide the state of that executable object to one or more other executable objects from the plurality of executable objects according to one or more state paths in response to a synchronization mechanism not defined within the description of the application.

Abstract: A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2.

Abstract: A method for operating a circuit (100) containing memristive devices (130) senses respective states of a plurality of memristive devices (130) and refreshes the respective states of the memristive devices (130) according to the states sensed. A memristive device (100) including an array of memristive devices (130) between crossing lines (110 and 120) includes logic that senses respective states of memristive devices (130) and refreshes the respective states of the memristive devices (130) according to the states sensed.

Abstract: One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

Abstract: Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse (1001). The method includes loading the N-bit codeword into a circular shift register (1002) and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse (1009).

Abstract: A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2.

Abstract: A method for operating a circuit (100) containing memristive devices (130) senses respective states of a plurality of memristive devices (130) and refreshes the respective states of the memristive devices (130) according to the states sensed. A memristive device (100) including an array of memristive devices (130) between crossing lines (110 and 120) includes logic that senses respective states of memristive devices (130) and refreshes the respective states of the memristive devices (130) according to the states sensed.

Abstract: One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

Abstract: An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances.

Abstract: In a programming model, a machine is represented in an object-oriented language by extending a Machine base class representing a state machine, to form a first class representing a first state machine. Each class extending the base class, includes at least one variable reflecting a state of the machine it represents. Also included are a method for receiving zero or more input parameters and advancing a state of the machine; a method for returning data reflecting a state of the machine; and an optional method that connects an output of one state machine to an input of another state machine. The state machines can be nested (as the classes extending the base class can be nested). A parallel program can be a single instance of a class extending the base class. All machine instances execute concurrently, regardless of where they are declared.

Abstract: A computer readable medium containing a computer program for representing an electronic circuit, which has been segmented into plurality blocks, as a routing-resource graph includes a first wiring data structure with first switch information and a first wire identity information to identify a first wire across a first plurality of blocks, a second wiring data structure with the first switch information and a second wire identity information to identify a second wire across a second plurality of blocks, and a first switch data structure having wire information and associated with the first and second wiring data structures for identifying a third wire connected to the first wire with a switch as a function of the first wire identity information and wire information from the first switch data structure.

Abstract: A computer readable medium containing a computer program for representing an electronic circuit, which has been segmented into plurality blocks, as a routing-resource graph includes a first wiring data structure with first switch information and a first wire identity information to identify a first wire across a first plurality of blocks, a second wiring data structure with the first switch information and a second wire identity information to identify a second wire across a second plurality of blocks, and a first switch data structure having wire information and associated with the first and second wiring data structures for identifying a third wire connected to the first wire with a switch as a function of the first wire identity information and wire information from the first switch data structure.

Abstract: A method for computation of truth tables is provided in which computing a truth table with N input variables includes the steps of: (a) providing N basis tables; (b) associating each one of the N basis tables with a corresponding one of the N input variables; and (c) performing logic operations on the N basis tables using a processor. Logic operations are performed on each bit of the each of the basis tables simultaneously.

Abstract: A method and system for network communication are provided which uses existing or new Agent Communication Language (ACL) with Structured Query Language (SQL) as the constraint language and extensible Markup Language (XML) for syntax. A communications network includes a server software module adapted to communicate with a machine user; an ACL interpreter adapted to communicate with the server software module; and a file system adapted to communicate with the ACL interpreter. The machine user sends requests to the server software module using an ACL with SQL as a constraint language.