Abstract: A magnetic resonance detection (MRD) system for and methods of detecting and classifying multiple chemical substances is disclosed. In one example, the presently disclosed MRD system is a nuclear quadrupole resonance (NQR) detection system that provides multi-frequency operation for substantially full coverage of the explosive NQR spectrum using a broadband transmit/receive (T/R) switch (or duplexer) and a single multi-frequency radio frequency (RF) transducer. More particularly, the MRD system provides a frequency-agile system that can operate over a wide band of frequencies or wavelengths. Further, a method of detecting and classifying various chemical substances is provided that includes pulse sequencing with “frequency hopping,” phase cycling for reducing or substantially eliminating background noise, and/or a process of mitigating amplitude modulation (AM) radio interference.

Abstract: A magnetic resonance detection (MRD) system for and methods of detecting and classifying multiple chemical substances is disclosed. In one example, the presently disclosed MRD system is a nuclear quadrupole resonance (NQR) detection system that provides multi-frequency operation for substantially full coverage of the explosive NQR spectrum using a broadband transmit/receive (T/R) switch (or duplexer) and a single multi-frequency radio frequency (RF) transducer. More particularly, the MRD system provides a frequency-agile system that can operate over a wide band of frequencies or wavelengths. Further, a method of detecting and classifying various chemical substances is provided that includes pulse sequencing with “frequency hopping,” phase cycling for reducing or substantially eliminating background noise, and/or a process of mitigating amplitude modulation (AM) radio interference.

Abstract: A current-mode D/A converter is described having variable output and offset control. According to an exemplary embodiment, a first D/A converter includes a number of first control inputs and an output capable of generating a first current proportional to a number of active first control inputs. A driver includes an input connected to the output of the first D/A converter, a number of second control inputs, and an output capable of generating a second current proportional to the first current based on a number of active second control inputs. A second D/A converter includes a number of third control inputs and an output capable of generating a third current proportional to a number of active third control inputs. Offset control circuitry includes an input connected to the output of the second D/A converter, an offset control input, and an output connected to the output of the driver.

Abstract: A current-mode D/A converter is described having variable output and offset control. According to an exemplary embodiment, a first D/A converter includes a number of first control inputs and an output capable of generating a first current proportional to a number of active first control inputs. A driver includes an input connected to the output of the first D/A converter, a number of second control inputs, and an output capable of generating a second current proportional to the first current based on a number of active second control inputs. A second D/A converter includes a number of third control inputs and an output capable of generating a third current proportional to a number of active third control inputs. Offset control circuitry includes an input connected to the output of the second D/A converter, an offset control input, and an output connected to the output of the driver.

Abstract: A peak detector is provided with a comparator and a storage capacitor coupled to the output of the comparator. An analog input signal is supplied via an input capacitor to the inverting input of the comparator. The non-inverting input of the comparator receives an output signal produced by an output buffer arranged in a feedback loop of the comparator. A level shifter is coupled in the feedback loop to dynamically adjust an input signal supplied to the output buffer in accordance with application requirements. The operation of the peak detector is controlled by non-overlapping clock signals supplied to switches at the input and inner feedback loop of the comparator to cancel offset caused by the comparator and output buffer.

Abstract: Briefly, in accordance with the embodiment of the invention, a refined timing recovery circuit for retiming a colored data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.

Abstract: Briefly, in accordance with one embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator. The digital-controlled oscillator includes an edge delay oscillator being adapted to produce digital oscillator pulses in response to digital clock pulses, each of the oscillator pulses having a rising edge and a falling edge. The edge delay oscillator is further adapted to delay at least one of the oscillator pulse edges in response to a delay signal. In accordance with another embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator, the oscillator including a clock having a substantially predetermined frequency. The oscillator is adapted to produce a digital output signal comprising a series of digital output pulses.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.