Abstract: A feedback control system, e.g. a voltage regulator, may include a control stage controlling an output stage that generates an output. The control stage may generate a control signal, e.g. a pulse-width modulated signal, having a duty-cycle and a switching frequency, and adjust the switching frequency when a present value of the duty-cycle differs from a most recent previous value of the duty-cycle, until the duty-cycle starts increasing, while also adjusting the duty-cycle according to the output. By adjusting the switching frequency, the (power) efficiency of the system may be optimized also regulating the output. The feedback system may also adjust the switching frequency according to an alternate algorithm to improve but not necessarily optimize the power efficiency by scaling a programmed frequency value using a scaling factor that is a function of a maximum duty-cycle value, a present frequency value, the programmed frequency value, and a minimum frequency value.

Abstract: The operation of a voltage regulator (or point-of-load regulator) may be optimized, by performing diode emulation using the low-side output transistor (LS FET). The voltage regulator may be monitored for a specified trigger event, which may include an averaged value of the load current dropping below a threshold value, and upon recognizing the trigger event, one or more of a number of possible diode emulation algorithms may be enabled. In one algorithm, the duty-cycle of the LS FET control signal may be set to a specified value, then adjusted until the duty-cycle of the high-side output transistor (HS FET) control signal settles and steady state is reached. The duty-cycle of the LS FET control signal may then be adjusted, and the duty-cycle of the HS FET control signal monitored, until the monitoring indicates that the duty-cycle of the HS FET control signal has reached a minimum value, thereby optimizing operation of the voltage regulator with respect to power loss.

Abstract: A method for optimizing operation of a feedback system may include generating a control signal according to a control parameter, regulating an output of the feedback system via the control signal, and monitoring the control parameter. In response to the monitoring indicating that the present value of the control parameter is outside a specific range of values, a first parameter that impacts an operating characteristic of the feedback system may be adjusted until the present value of the control parameter is within the specific range of values. The specific range of values of the control parameter may correspond to a target level of the operating characteristic of the feedback system with respect to the first parameter.

Abstract: Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system.

Abstract: Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system.

Abstract: Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system.

Abstract: A method and system are disclosed for spreading the power associated with digital signals being transmitted to reduce electromagnetic interference (EMI) emissions by receiving, via a first transmission line, a first power spread signal representative a first digital signal modified using a first power spreading digital noise signal, modifying the power spread signal using a second power spreading digital noise signal substantially similar to the first power spreading digital noise signal to generate a second digital signal substantially similar to the first digital signal, modifying the second digital signal using a third power spreading digital noise signal to generate a second power spread signal and providing the second power spread signal for output to a second transmission line.

Abstract: A method and system is disclosed for spreading the power associated with digital signals being transmitted to reduce electromagnetic interference (EMI) emissions by receiving, via a first transmission line, a first power spread signal representative a first digital signal modified using a first power spreading digital noise signal, modifying the power spread signal using a second power spreading digital noise signal substantially similar to the first power spreading digital noise signal to generate a second digital signal substantially similar to the first digital signal, modifying the second digital signal using a third power spreading digital noise signal to generate a second power spread signal and providing the second power spread signal for output to a second transmission line.

Abstract: Transmit-side active signal management circuitry applies one or more active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuitry applies one or more corresponding active signal management processes, as appropriate, to the received digital signal to recover the information represented by the original digital signal. The interconnect can include a cable used to transmit the signals between a source device and a destination device, whereby one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry is implemented at a corresponding cable receptacle of the cable. Alternately, one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry can be implemented at a cable adaptor, thereby permitting the use of a passive cable interconnect to transmit the signal.

Abstract: Transmit-side active signal management circuitry applies one or more active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuitry applies one or more corresponding active signal management processes, as appropriate, to the received digital signal to recover the information represented by the original digital signal. The interconnect can include a cable used to transmit the signals between a source device and a destination device, whereby one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry is implemented at a corresponding cable receptacle of the cable. Alternately, one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry can be implemented at a cable adaptor, thereby permitting the use of a passive cable interconnect to transmit the signal.

Abstract: A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.

Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port.

Abstract: A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The bridge includes master and slave capability on both buses and an arbiter for selecting between requests from bus masters on one bus. The data buffer includes a number of dual ported memories for write posting and read ahead operations. Each dual ported memory is allocated to a bus master of the one bus. The bridge allows data operations to each dual ported memory based on data or space availability of the memory. Simultaneous reading and writing capability on alternate buses is provided.

Abstract: A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The data buffer includes a number of dual ported memories for write posting and read ahead operations. The data buffer further includes address incrementing and comparison circuitry to synchronize the flags into the clock domain of each bus.

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM.

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycles to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM.

Abstract: A process for producing a superconducting ceramic material using microwave energy and the superconducting ceramic material produced thereby. A preferred process comprises the steps of mixing powders of Y.sub.2 O.sub.3, CuO and at least one member selected from the group consisting of BaCO.sub.3 and BaO, and then subjecting the resultant powder mixture to heat treatment in microwave energy. In a preferred embodiment, the heat treatment step comprises the steps of calcining, sintering and annealing, at least one of the calcining and annealing steps using microwave energy.